65 nm data verified. How about the 45 nm data?
"A 65nm Logic Technology Featuring 35nm Gate Lengths, Enhanced Channel Strain, 8 Cu Interconnect Layers, Low-k ILD and 0.57 pmZ SRAM Cell"
P. Bai, C. Auth, S. Balakrishnan, M. Bost, R. Brain, V. Chikarmane, R. Heussner, M. Hussein, J. Hwang, D. Ingerly,
R. James, I. Jeong, C. Kenyan, E. Lee, S-H. Lee, N. Lindert, M. Liu, Z. Ma*, T. Marieb’, A. Murthy, R. Nagisetty,
S. Natarajan, J. Neirynck, A. Ott, C. Parker, J. Sebastian, R. Shaheed**, S. Sivakumar, J. Steigenvald, S. Tyagi,
C. Weber**, B. Woolely*, A. Yeoh, K. Zhang, and M. Bohr
Portland Technology Development, * QRE, ** TCAD, Intel Corporation. Hillsboro, OR 97124, USA
Contact: pene.bai@,intel.com |
