Toshiba outlines NAND roadmap amid MCP launch
siliconstrategies.com
SAN JOSE, Calif.--Amid disclosing its roadmap in the NAND flash arena, Toshiba Corp. Monday (May 10) rolled out a multi-chip package (MCP) solution that includes a pair of new, low-power devices.
Toshiba's new 1.8-volt, MCP solution is said to support a combination of NAND flash, SRAM, and SDRAM devices in a small chip-scale package (CSP). The MCP also supports two new devices from Toshiba, including separate 1.8-volt, burst-mode NOR flash and pseudo SRAM chips.
With its new MCP, the company claims it can provide OEMs with the required pieces for advanced 2G and 3G cellular phones. And unlike many of its rivals, Toshiba can provide both NAND- and NOR-based flash memory devices in the same package. The company's NAND-based flash memory is built around its multi-level cell (MLC) technology.
The new MCP can be offered in two- to six-die stack configurations, plus up to three spaces, said Scott Beekman, business development manager for communications memory products at Toshiba's U.S. sales arm, Toshiba America Electronic Components Inc., based in Irvine, Calif. "The MCP enables customers to meet new form-factor and system requirements," Beekman said in an interview with Silicon Strategies.
Today's cellular phones require varying combinations of memory chips in smaller packages to maximize handset performance, according to Toshiba. Cell-phone manufacturers require NOR flash for code storage and SRAM and PSRAM for working memory. OEMs use NAND flash in addition, or in place of NOR, because of the technology's write/erase speeds for data storage.
Toshiba's new 1.8-volt NOR and PSRAM devices both offer burst-mode capabilities, which enable the phone to read and write larger files at faster rates. The new 128-megabit NOR device is a 8-Mbit x 8 chip with 10-ns access times.
The 128-Mbit PSRAM offers a standby mode that requires only 200 microamps of current. The 8-Mbit x 8 part will be offered within the MCP solution or as a discrete component in a 12 x 9 PFBGA package. The NOR device will initially be offered only in within the MCP.
A key to Toshiba's MCP strategy is its NAND flash offerings. The new MCP can be configured with either 256- or 512-Mbit parts, based on a 130-nm process and MLC technology.
SLC vs. MLC
MLC NAND flash allows each memory cell to store two bits of information, as compared to one bit per cell for rival single-level cell (SLC) technology. SLC NAND flash is rated at 100,000 write/erase cycles. In comparison, MLC NAND is rated at about 10,000 cycles.
For many applications, however, SLC NAND is "overkill," said Scott Nelson, director of memory marketing for Toshiba America. "SLC is faster, but consumers will not be able to tell the difference," Nelson said. "There are certain applications that want SLC. Most consumer applications can benefit from MLC."
The rival NOR crowd, especially Intel Corp., is pushing this technology for both the code and data storage market. "When you hit the 1-megapixel threshold (for camera phones), you really need NAND, because of the data storage capabilities," Beekman said. "NOR doesn't even come close for data storage."
"MLC NAND is also scalable," Nelson added. "Our roadmap is very aggressive."
Last month, in response to Samsung Electronics Co. Ltd.'s efforts in the 90-nm SLC NAND flash arena (see April 1 story), Toshiba and its partner, SanDisk Corp., jointly rolled out its initial line of MLC NAND-based flash memory devices, based on 90-nm technology.
The companies rolled out two devices, including the industry's first 4-gigabit single-die, MLC NAND chip. Toshiba also announced an 8-Gbit NAND flash memory IC that stacks two of the 4-Gbit NAND flash memories in a single package (see April 5 story).
The chips are based on the company's "large block" page/block technology. In 2004, Toshiba is also expected to roll out three other NAND devices, based on its 90-nm process and "large block" technologies. The three monolithic devices include 512-Mbit, 1-Gbit, and 2-Gbit products, according to the company's roadmap.
In 2005, the company is scheduled to debut 1-, 2-, 4-, 8-, and 16-Gbit NAND flash devices, based on a 70-nm process. The 8-Gbit device stacks two 4-Gbit chips, while the 16-Gbit product stacks two 8-Gbit products, according to the company's roadmap. It appears that Toshiba will roll out the 4-, 8-, and 16-Gbit devices first, followed by the 1- and 2-Gbit products.
Then, in mid-2006 or 2007, Toshiba is slated to produce a 16-Gbit device, based on a 55-nm process, according to the roadmap. These new chips will be produced at Toshiba's Yokkaichi Operations in Japan. Yokkaichi Operations is also the site of the new 300-mm wafer fabrication facility. Mass production for the 300-mm fab in Yokkaichi is expected to start in the second half of 2005. |
