Monday October 2, 9:01 am Eastern Time
Press Release
SOURCE: Mentor Graphics Corporation
Mentor Graphics Announces Availability of FastScan 2001
Major Enhancements Provide Designers With a Design-for-Test Solution That Handles Next-Generation Requirements
INTERNATIONAL TEST CONFERENCE, ATLANTIC CITY, N.J., Oct. 2 /PRNewswire/ -- Mentor Graphics Corporation (Nasdaq: MENT - news) announced today its latest automatic test pattern generation (ATPG) tool, FastScan(TM) 2001. FastScan 2001 contains significant new functionality that reduces test pattern sizes by as much as 60 percent and also provides new capabilities for testing small embedded memories and other macros that are common in today's system-on-chip (SoC) designs. These new features play a significant role in reducing the total cost of test as well as improving overall test coverage for microprocessor designs, ASICs, and application-specific standard products (ASSPs).
Reducing Test Patterns
The trend to multi-million gate designs is resulting in test vector sets that are exceeding limits of the Automatic Test Equipment (ATE) or limits set by ASIC vendors or foundries. Companies are faced with costly ATE upgrades or the need to truncate the test patterns, which results in reduced fault coverage and can compromise product quality. FastScan 2001 delivers new ATPG pattern compression capabilities specifically targeted at designs that contain multiple clocks, now standard in telecom, wireless and networking applications. With this new multi-clock compression capability, FastScan 2001 delivers significant value to ASIC and fabless semiconductor designers by allowing them to stay within maximum testing limitations set by their ASIC vendor or foundry without adding additional cost or truncating test patterns.
Testing Embedded Blocks
Complex SoC designs today often include hundreds of small embedded memories that are not large enough to justify built-in self-test (BIST) approaches. Often these blocks as well as the surrounding shadow logic remain untested, reducing the overall test coverage. FastScan MacroTest offers unique DFT capabilities that allow designers to automatically test these small, embedded memory blocks and the shadow logic using existing scan chains. FastScan 2001 extends the capabilities of MacroTest by adding support for synchronous macros (e.g., synchronous RAM). As a result, FastScan MacroTest can now be used on a broader set of designs, enabling designers to improve test coverage and product quality without adding additional test logic.
``We have seen a growing need for DFT tools to meet more demanding quality, time-to-market and test cost goals across all segments of the market,'' said Fred Cohen, general manager of the Mentor Graphics® Design-for-Test division. ``The enhancements we are delivering with the FastScan 2001 ATPG solution will simply enable our customers to deliver higher quality products at a lower cost.''
Handling Next-Generation Designs
Additional enhancements available with FastScan 2001 include:
Fault Sampling: Allows users to quickly sample a percentage of the entire fault list for a design in order to assess the coverage and/or testability issues of a circuit. Internal studies on customer designs of 1 million gates and above indicate that a 1 percent sample estimates coverage to within 1 percent of the final coverage for the entire design.
K-shell Command Line Environment: Provides a K-shell command line environment that enables designers to easily recall previous commands for re-execution, allows for easy editing of command line arguments, and provides a command history mechanism.
Pricing and Availability
FastScan 2001 will be available for production shipment in October 2000. Mentor Graphics customers presently on a FastScan support program will receive an upgrade to FastScan 2001 at no additional cost. FastScan 2001 is available through Mentor Graphics starting at $92,400. The MacroTest option is available for an additional $50,000. For more information regarding FastScan 2001 and the complete portfolio of Mentor Graphics ATPG and BIST products, please visit the Mentor Graphics DFT web site at www.mentor.com/dft.
About Mentor Graphics
Mentor Graphics Corporation is a world leader in electronic hardware and software design solutions, providing products and consulting services for the world's largest electronics and semiconductor companies. Established in 1981, the company reported revenues over the last 12 months of more than $500 million and employs approximately 2,600 people worldwide. Corporate headquarters are located at 8005 S.W. Boeckman Road, Wilsonville, Oregon 97070-7777, Silicon Valley headquarters are located at 1001 Ridder Park Drive, San Jose, California 95131-2314. World Wide Web site: www.mentor.com.
NOTE: Mentor Graphics is a registered trademark of Mentor Graphics Corporation. FastScan is a trademark of Mentor Graphics Corporation. All other company or product names are the registered trademarks or trademarks of their respective owners.
Mentor Graphics can be found in booth # 809 at the International Test Conference
CONTACT: Leanne White of Mentor Graphics Corporation, 503-685-1984, or leanne_white@mentor.com; or Jason Khoury of Benjamin Group/BSMG Worldwide, 415-352-2628, or jason@benjamingroup.com, for Mentor Graphics Corporation.
SOURCE: Mentor Graphics Corporation |
