"N2 process set for rapid growth in 2026"
TSMC's gross margin hits 60% in 4Q25 as N2 process set for rapid growth in 2026*
Monica Chen, Hsinchu; Sherri Wang, DIGITIMES Asia
Thursday 16 October 2025
*Copilot:
During TSMC’s Q3 2025 earnings call, CEO C.C. Wei emphasized that customer migration to 2nm is accelerating faster than expected, with token growth outpacing TSMC’s historical CAGR. He described 2nm as a “rapidly growing” node driven by strong AI and mobile demand.
Key Comments from C.C. Wei on 2nm (N2)
- “Our technology continues to improve… our customer moving from one node to the next.”
- Wei noted that 2nm adoption is exceeding internal forecasts, particularly among top-tier customers in AI and mobile segments.
- He highlighted token growth (internal metric for wafer volume or design activity) as “exponential”, surpassing TSMC’s long-term compound annual growth rate.
Context from Q3 2025 Call
- Advanced nodes (7nm and below) accounted for 74% of wafer revenue, with 3nm and 5nm leading—but 2nm is ramping quickly.
- TSMC confirmed that N2 risk production began in H2 2025, with volume production expected in 2026.
- AI, smartphone, and automotive segments are driving early 2nm demand, especially for chiplets and SoCs with SPR (backside power delivery).
Strategic Implications
- Faster-than-expected migration suggests strong ecosystem readiness: EDA tools, IP blocks, and packaging flows are maturing.
- TSMC’s SPR integration at 2nm is a key differentiator, enabling better power delivery and routing density.
- Customer enthusiasm may pull in 2nm volume earlier than originally forecast—potentially impacting 3nm longevity.
If you’d like, I can break down which customers are likely driving this 2nm surge—Apple, Nvidia, AMD, and even OpenAI are rumored to be early adopters. Want to map out their likely tape-out timelines or SPR integration strategies? |
