SI
SI
discoversearch

We've detected that you're using an ad content blocking browser plug-in or feature. Ads provide a critical source of revenue to the continued operation of Silicon Investor.  We ask that you disable ad blocking while on Silicon Investor in the best interests of our community.  If you are not using an ad blocker but are still receiving this message, make sure your browser's tracking protection is set to the 'standard' level.
Technology Stocks : Advanced Micro Devices - Moderated (AMD)
AMD 221.06-1.1%Jan 5 3:59 PM EST
 Public ReplyPrvt ReplyMark as Last ReadFilePrevious 10Next 10PreviousNext  
To: Tenchusatsu who wrote (53278)8/31/2001 11:06:37 AM
From: pgerassiRead Replies (2) of 275872
 
Dear Tench:

You have better read up on P4 technical documentation then. The P4 can decode one x86 instruction per cycle. The trace cache can only issue up to 6 micro ops per cycle from the trace cache and there are severe restrictions required for that. Two micro ops must be integer add/sub ops suitable for half cycle issue, two micro ops must be integer add/sub, logic, branch or store ops suitable for half cycle issue, 1 micro op must be for memory loads and 1 micro op must be for memory stores. No floating point, MMX or SSE(2) ops, moves, loads, or stores are allowed. And that only from the trace cache. The decode sequence will probably never allow that to occur and given the stores and loads, the cache subsystem will stop it from occurring more than once in a long while. Matter of fact, two consecutive floating point ops including SSE(2), can only be executed one after the other or one per cycle.

Athlon can decode 3 direct or 1 vector x86 instructions per cycle into 6 micro ops which can be on average be mostly executed all at once. And two floating point ops plus a floating store or load can be executed at once far higher than P4. The total number of Tbird execution pipelines are 9. P4 has 4. Palomino may have at least one more, HWP. The P3 can decode 1 complex or 2 simple x86 instructions per cycle (although the definition is not the same as Athlon).

Thus you are incorrect, Athlon is the only x86 CPU IIRC which can decode 3 x86 instructions per cycle. The P3 could do 2 and the P4 can only do 1.

Pete
Report TOU ViolationShare This Post
 Public ReplyPrvt ReplyMark as Last ReadFilePrevious 10Next 10PreviousNext  

HomeMailHotSubjectMarksPeopleMarksKeepersSettings
Terms Of UseContact UsCopyright/IP PolicyPrivacy PolicyAbout UsFAQAdvertise on SI
© 2026 Knight Sac Media.  Data provided by Twelve Data, Alpha Vantage, and CityFALCON News