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Chiplet-Based Solutions Accelerate the Development of Embedded NVM
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 Maurizio Di Paolo Emilio
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Deca Technologies and Silicon Storage Technology (SST), a subsidiary of Microchip Technology Inc., have announced a strategic collaboration to address the challenges of semiconductor integration through non-volatile memory (NVM) chiplet solutions. This partnership combines Deca’s M-Series fan-out and Adaptive Patterning technologies with SST’s SuperFlash embedded flash technology, creating what both companies describe as a comprehensive platform for modular, multi-die systems.
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In an exclusive interview with Embedded.com, Dave Eggleston, Senior Business Development Manager at Microchip Licensing Division, will delve into the details and implications of the announced partnership.
 Dave Eggleston, Senior Business Development Manager at Microchip Licensing Division
Why a chiplet-based approach?Eggleston, who has decades of experience commercializing various NVM technologies, explained the reason for the chiplet approach: “For our customers, the time required to develop and qualify embedded NVM can be as much as five years”.
This timeline creates a significant bottleneck for companies working with leading-edge logic nodes. “I’ll use an example of an automotive customer I have today that’s doing an automotive controller at 55nm. They started to look at their next-generation chip that they’re going to do. It’s at 5nm now. That’s a huge jump from 55 to five. But they did that because of the digital logic they want to put in. And they’re saying, ‘Well, where do I get my code storage from? Where do I get my data storage from?’ And that was where a NVM chiplet starts to make a lot of sense.”
Beyond advanced node challenges, the chiplet approach addresses another critical need in specialized process technologies. In the BCD market specifically, there’s a growing trend toward consolidating what were previously two-chip solutions into single-chip implementations, making integrated NVM capability increasingly valuable.
The Deca advantage: cost and flexibilitySelecting the right assembly technology proved crucial to making chiplet-based NVM economically viable for the target markets. Eggleston notes, “We know we can’t take the same approach as server processors. It’s too expensive, and in many cases, that involves an organic substrate or silicon substrate for connecting the die. In the microcontroller market, tens of cents is a lot, so we need to be single pennies or fractions of a penny.”
Wafer-to-wafer bonding, while effective for some applications, presented its own limitations, such as matching the size of dies developed with different process modes (e.g., a digital logic at 12nm with a flash memory at 28nm).
Deca’s redistribution layer (RDL) technology emerged as the solution that satisfied these requirements. “In 2D, you place a big and a small die next to each other. The mold compound actually becomes the substrate holding them, and they’re kind of face up. On the redistribution layer, you deposit the material to interconnect them. The advantage is that this is a very low-cost solution because you don’t have the substrate”, said Eggleston.
Moreover, the relevant size of Deca’s panel-level processing (600 mm x 600 mm) enables the scalability of this technology.
Adaptive patterning solves the alignment challengePerhaps the most innovative aspect of Deca’s technology is how it handles the misalignment that occurs during die placement. “How do you handle this misalignment? Deca has a unique IP, named adaptive patterning, that addresses this issue. They take a very high-resolution image of the panel, and they make adjustments in software for the redistribution”, said Eggleston.
This software-driven compensation approach represents a different way of thinking about manufacturing precision. Rather than demanding perfect mechanical placement, the system accommodates real-world variations through intelligent adaptation.
 Multiple 2µm die-to-die wires detected at different die-shift conditions with Adaptive Patterning (Source: Deca Technologies Inc.)
Technical challengesA key factor of any chiplet solution is the interface design, which defines how the dies communicate with each other. “In embedded flash, we use an extensive I/O interface, supporting down to eight-nanosecond read speed”, said Eggleston.
The chiplet approach enables SST to maintain the wide-bus architecture customers expect from embedded flash. “With a chiplet, you can get the same interface that you have in embedded flash, with more flexibility and scalability”, said Eggleston. The interconnect delay through the RDL proved surprisingly minimal, at about 10 picoseconds.
Another significant technical hurdle in chiplet design involves simulation and verification across different process technologies. “It gets more complicated when you’re talking about two different process technologies, potentially from two different foundries. How can I do that simulation, and in a way that covers all the electrical, thermal, environmental, and mechanical stress?” said Eggleston. This challenge led SST to develop comprehensive simulation capabilities as part of its offering.
The end result is a full approach that uses industry-standard tools set up in certain ways and specialized simulation files made during several design cycles. This is not only a chance to buy technology, but also a chance to learn from it. It supports SST’s two business models of selling chiplets and licensing IP together with design skills.
Target markets and future applicationsThe automotive market is the primary focus for chiplet-based NVM solutions. Eggleston underscores the flash memory’s advantages in this demanding application: “One of the strongest areas for SST SuperFlash has been and continues to be automotive. We can do automotive-grade one, we can do automotive-grade zero. We can do it at full performance, for reliability, there’s no derating in reliability for automotive”.
An emerging application area involves the use of flash memory for AI inference. “We’ve developed a way to do edge inference at very low power, using SST SuperFlash. This is a completely different usage of the flash memory cell, employed to store the vectors needed for inference processing”, explained Eggleston.
The chiplet approach proves particularly valuable here due to the growth of AI models. As AI models are advancing rapidly, more vectors and advanced models are required. “To a digital logic of a certain SoC, we can add a chiplet of flash memory, doing this inference processing. And then I can add more chiplets, depending on the size of the AI models I want to support”, stated Eggleston.
The path forwardEggleston’s vision for chiplet adoption in the microcontroller and embedded industries is as follows: “I see mainstream, high-volume MCUs remaining fully integrated, single pieces of silicon. But I see the more performant SoCs, those that need or want to push into more advanced digital logic, adopting a chiplet approach.”
The FPGA analogy came naturally: “Let me compare it to FPGAs. ASICs are lower cost. It’s a single piece of silicon. Who would ever need an FPGA? Nevertheless, there’s still a really big FPGA market because of those exact same things. I can get faster time to market, I can do more things, I can experiment”, said Eggleston.
He added that, for now, the focus is still on specific customer deployments and on growing expertise. “We’re doing specific implementations for customers, one step at a time, just for their environment.” This practical strategy, which solves real problems for real customers while moving toward bigger platforms, could be the best way for chiplet technology to be adopted in places where cost is a big concern. |
