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Politics : Formerly About Advanced Micro Devices
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To: Charles R who wrote (102520)4/6/2000 1:27:00 AM
From: Scumbria  Read Replies (1) of 1575765
 
Chuck,

The largest cache wins. If Athlon delivers a larger L1+L2 than Willy, the IPC may be higher. However, the effect of SSE preload instructions used by Intel's compilers should not be underestimated. The high Spec scores that Elmer keeps reminding us about are due largely to these instructions.

Do you not expect an architecture with additional functional units to benefit more from a fairly deep reorder unit and high bandwidth on board cache? (this compared to the current generation products where the additional functional units are clearly not paying off)

Not really. x86 instruction streams have too many hazards and dependencies to do much out of order execution. Having lots of execution units impresses Microprocessor Forum audiences, but does little for performance.

Scumbria
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