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Politics : Formerly About Advanced Micro Devices

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To: Scumbria who wrote (102526)	4/6/2000 1:58:00 AM
From: Charles R	Read Replies (1) of 1575980

Scumbria, <It is hard to find more than 2 or 3 instructions at a time in an x86 instruction stream without dependencies. > Agreed. A decade back, when I did some hands on CPU work, we used a branch per 5 instructions as the rule of the thumb. (what is this number on x86 code anyway?). So, in the implementation we had, regardless of any hazards, it was pretty clear to us that there was no point going past that number for execution units. (I am talking about integer code here - not including FPU/MMX stuff here) I see most modern processors staying with 2-4 integer units (including load/store) so clearly there is uniformity of agreement in the architectural community on this issue. (Wilamette implementation seems really clever.) When I am talking about is not a huge jump because of the incremental units. The difference I am talking about is more subtle. I am talking about IPC going from say 1.6 to 1.7 because of the impact of low latency cache on additional functional units. Chuck P.S.: I don't want to beat this to death so I will see what you have to say and call it a nite.

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