SI
SI
discoversearch

We've detected that you're using an ad content blocking browser plug-in or feature. Ads provide a critical source of revenue to the continued operation of Silicon Investor.  We ask that you disable ad blocking while on Silicon Investor in the best interests of our community.  If you are not using an ad blocker but are still receiving this message, make sure your browser's tracking protection is set to the 'standard' level.
Politics : Formerly About Advanced Micro Devices

 Public ReplyPrvt ReplyMark as Last ReadFilePrevious 10Next 10PreviousNext  
To: ptanner who wrote (106768)4/19/2000 2:42:00 AM
From: Tenchusatsu  Read Replies (3) of 1574061
 
Thread, just FYI regarding Celeron:

The 0.18u Celerons isn't just a Coppermine with half the cache disabled, according to Anandtech:

anandtech.com

Basically, Coppermine-128 (the 0.18u Celeron) has half the cache as Coppermine-256. Also, the L2 cache on Cumine-128 is 4-way set-associative, instead of 8-way. Furthermore, for some reason or other, the L2 latency on Cumine-128 is longer than Cumine-256. I don't know why.

Normally, I'd be posting this on the INTC thread, but I figured you AMD guys would care more than the other guys.

Tenchusatsu
Report TOU ViolationShare This Post
 Public ReplyPrvt ReplyMark as Last ReadFilePrevious 10Next 10PreviousNext