SI
SI
discoversearch

We've detected that you're using an ad content blocking browser plug-in or feature. Ads provide a critical source of revenue to the continued operation of Silicon Investor.  We ask that you disable ad blocking while on Silicon Investor in the best interests of our community.  If you are not using an ad blocker but are still receiving this message, make sure your browser's tracking protection is set to the 'standard' level.
Technology Stocks : C-Cube
CUBE 36.52+0.3%Dec 12 9:30 AM EST

 Public ReplyPrvt ReplyMark as Last ReadFilePrevious 10Next 10PreviousNext  
To: DiViT who wrote (10911)3/3/1997 4:17:00 AM
From: Baggins   of 50808
 
Hi David! NTSC Encoder doesn't have to be all that big if composite
signal is generated digitally. Then all that's left to do is send it to a 9 or 10 bit DAC and voila! The analog circuits are not necessarily yield killers if designed for the process (ordinary CMOS will do). On the other hand analog circuits tend not to shrink very well unless one takes an area hit by oversizing the devices to begin with. Also original and target process need to have similar parametrics so that critical component values don't vary too much. For example if well resistors are used in reference circuits, it would be helpful if their resistivity didn't vary too much from process to process. In any case it is difficult to design the analog circuits for
a future shrink without knowing the process characteristics of the future process. This is not too likely given that the current process is TSMC digital CMOS. On the other hand one could leave a few spare components lying around on chip and rewire things with a metal mask change. This sort of tweaking could be accomodated rather quickly and with a fairly good confidence level. Sorry, I think I'm running on a bit here ...
Report TOU ViolationShare This Post
 Public ReplyPrvt ReplyMark as Last ReadFilePrevious 10Next 10PreviousNext