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Politics : Formerly About Advanced Micro Devices
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To: pgerassi who wrote (109556)5/7/2000 12:14:00 AM
From: Ali Chen  Read Replies (1) of 1576606
 
Pete, <12 cycle latency becomes 8 cycle latency>

Latency, as seen from a CPU and overall performance
standpoint, is defined as a delay between a moment
of memory read request and the first "critical"
data. Your calculations are based on incorrect
definition and therefore are irrelevant.

<No FSB change is involved.>
That's exactly where the problem is, as
it was explained in my previous post.

<It should be clear that DDRSDRAM will improve
latency by transferring a cache line faster.>
No. What is important for performance is the
critical word, or the data the processor
needs right now, to avoid waste of processing
clocks. Although the cacheline gets transferred
faster, the other data in that cacheline are
not in urgent need at that particular instance,
and hence do not affect the performance much.

- Ali
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