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Politics : Formerly About Advanced Micro Devices
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To: Gopher Broke who wrote (111665)5/20/2000 4:01:00 PM
From: Charles R   of 1574258
 
Gopher Broke,

<Any hardware experts out there who can comment on the effect this bus synchronization through the northbridge might have on memory latency?>

Depending on the implementation it could save at least a clock or two in the chipset. Since these are 100 or 133 MHz clocks, the savings is significant in terms of CPU clock cycles.

May be someone with a more firsthand knowledge of AMD and VIA chipsets can comeup with a precise number.

Chuck
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