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Politics : Formerly About Advanced Micro Devices
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To: Joe NYC who wrote (113142)5/29/2000 3:27:00 AM
From: Joe NYC  Read Replies (1) of 1575627
 
Thread,

Since nobody commented on my repost of the Yahoo post re: AMD presentation at DDR summit, here is something significant that I would like to highlight:

We'll introduce support for DDR memory, and what's very interesting is you can see here that both the host bus and the DDR memory are both operating at the same speeds. They're both operating at 266, or in case of lower performance systems, 200 megahertz, but the significant thing is they're running synchronously.

From a system design point of view this is the path in the architecture of the platform that you want to optimize. You want to make sure that your processor to memory path is the most optimized, most straight through. This is actually very unusual to see. If you look in the path there is always typically a mismatch. Now we have actually addressed this by creating a matched pair. We have two DDR buses running at 266 megahertz, both 64 bits wide.

This allows the north bridge to have a very straightforward low latency path to create high system performance.

Can you say BX class chip cor Athlon? I think this is the reason all the other chipsets fall short of BX: They are not synchronous.

My guess is that 760 will provide bigger boost in performance than Thunderbird will over Athlon classic.

Joe
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