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Politics : Formerly About Advanced Micro Devices

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To: Duncan Baird who wrote ()6/4/2000 1:07:00 PM
From: milo_morai  Read Replies (2) of 1576333
 
AMD spins Athlon die with exclusive L2 cache
Jun. 02, 2000 (Electronic Engineering Times - CMP via COMTEX) -- SAN MATEO,
CALIF. - Advanced Micro Devices Inc. has integrated a Level 2 cache in the
latest incarnation of its Athlon processor but will not charge a premium for the
improved device. The pricing strategy is part of the company's continued battle
for dominance in the processor market.

For the moment AMD is neck-and-neck with Intel Corp. in terms of raw processor
performance, but analysts said the new class of Athlon chips may fall behind in
the performance race when Intel brings out its Willamette device later this
year.

AMD is introducing the newest Athlon design in both the Slot A format and a new,
socket-based form factor called Socket A. Both are available now in speeds
ranging from 750 MHz to 1 GHz, and all versions feature 256 kbits of on-die L2
cache. In addition to the new Athlons, which were designed under the code-name
Thunderbird, the company has started its first volume shipments of its new Duron
processor
, a low-cost device positioned against Intel's Celeron. And AMD has
shipped its first volume batch of products from its new fab in Dresden, Germany.


"I think we have had near-flawless execution in the past year," said Mark Bode,
division marketing manager for the company's Athlon unit, based in Austin,
Texas. "AMD today is very different from the AMD of a year ago."


Pacing Intel

A year ago, AMD was poised to unveil its first Athlon device, which was
considered a make-or-break product. The company was losing money nearly every
quarter and had been consistently plagued by an inability to deliver enough of
its fastest processors to remain profitable.

The Athlon rollout has since proved successful, with hardly any of the
manufacturing glitches that had seemed part and parcel of the preceding K6 line.
AMD is now seen as running alongside industry leader Intel in processor
performance.

Besides integrating the L2, AMD has shifted the cache architecture to an
exclusive cache design. Many of the current generation of processors with on-die
L2, including those from Intel, use an inclusive cache architecture, in which
the entire contents of the Level 1 cache is mirrored in the L2. AMD's approach
does not duplicate the L1, so there is more space to store information in the
L2.

"This is an improvement," said Dean McCarron, principal analyst for Mercury
Research (Scottsdale, Ariz.). While he characterized the use of the exclusive
cache architecture as a small step forward, he said it is more significant than
a simple bump up in speed grades. "This translates to better use of the cache
memory."

Another performance boost will come from increasing the frequency of the
secondary cache. The integrated cache runs at the same speed as the processor
core. The off-die Athlon cache was originally intended to run at half the speed
of the processor. But Bode said off-die cache speeds have reached a ceiling in
the mid-300-MHz range. Chips with processor cores exceeding 700 MHz have
suffered a performance hit because the L2 cache runs at less than half the speed
of the processor core. McCarron said one recently produced 1-GHz Athlon featured
a 350-MHz cache-just a bit better than one-third the speed of the core.

Although analysts consider the Athlon and Pentium III roughly comparable at
equivalent speed grades, depending on which benchmarks are compared, Intel may
pull ahead in the performance race before year's end with its upcoming
Willamette chip. That processor will feature a front-side bus that reaches
speeds of up to 400 MHz and interfaces only with Rambus DRAM. The current Athlon
bus runs at 200 MHz, but the road map calls for a chip set later this year that
will support both a 260-MHz bus and the use of double-data-rate DRAM.


Pricing plays

Last year, as AMD struggled to deliver chips that were still not as fast as
Intel's best offering, Intel devised a marketing strategy of undercutting AMD on
pricing for any chip for which AMD offered the same speed grade. Intel
maintained high prices in areas where AMD was not a threat, thereby keeping
average margins up and the revenue stream healthy. To remain competitive, AMD
was forced to cut prices on its leading products, and it posted significant
losses as a result.

Analysts are now questioning whether Intel can follow the same strategy with the
Willamette. Market demand has been tepid thus far for systems based on the very
fast but very expensive Rambus memory platform. If demand for Willamette-based
systems is weak, it may not matter whether the device outperforms the Athlon,
and the front lines in the microprocessor marketing battle will continue to pit
the Athlon against the Pentium III.


eetimes.com


-0-

By: Will Wade
Copyright 2000 CMP Media Inc.

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