AMD sees the technology as being extended "up" into a point-to-point connection for servers, eliminating the microprocessor bus entirely. For 32-bit Athlon multiprocessor systems, a superset of the LDT specification, or "coherent LDT," has been developed for non-uniform memory-access matrixes, where arrays of processors can access dedicated local memory as well as "distant" memory that is attached to other CPUs.
Basic LDT I/O passes data in a single direction, using either 2-, 4-, 8-, 16-, or 32-bit wide connections, which works out to 100 Mbits per second per bit-wide connection. An 8-bit-wide connection transfers 800 Mbytes in one direction. The coherent LDT specification doubles the bandwidth to 1.6 Gbits/second.
techweb.com
Fascinating. So while Intel has shot itself in the foot with Rambus, an unfortunate attempt to improve upon a 1,066 Mbyte/sec memory bottleneck (PC133), AMD has easily outdone that effort with DDR and has been working on improving the 132Mbyte/Sec PCI bottleneck with a network and disk i/o bus that can run at up to 3,200Mbyte/Sec for point to point DMA (6,400Mbyte/Sec for Coherent LDT). If they get Adaptec on board so they can offer RAID and network controllers, and incorporate this i/o bus into a NUMA MPU architecture, it would be competitive with anything else being planned. No wonder why IBM, Alpha, and SUN have appeared a bit cooler towards AMD lately. It's easy to forget that this platform is being targeted at AMD's SHV 64 bit processors.
It's a helluva bet - at some point they'll have to lay down their cards and we'll see if they were bluffing or not.
Dan |
