Bill: Slot1, <there must be more to it>. The mechanical design is not an issue. The main feature of Slot1/Socket8 is in new logical and electrical interface.
In logic, the Slot1/8 uses deeply pipelined bus transactions, up to four. In combination with sufficient buffering, this allows for write-back operations to occur in parallel with accesses to backside L2 cache, which effectively doulbles the CPU i/o bandwidth. On the dark side, this appers to be the maximum they can get out of bus, so any increase in bus speed does not add any system performance...
Electrically, in slot1/8 Intel uses the GTL+ signalling, which uses single reference voltage instead of two thresholds as in TTL signalling. This lowers the voltage swing but require more pins to distribute and maintain this reference voltage across the chip/connector.
Please notice the (+) suffix to GTL. This is a typical market protection scheme for Intel - take/buy a well-known interface, and make a proprietary modification, maybe making is worse but proprietary, and twist the industry using their monopolistic power. The same is happening with RAMBUS - they are buying their technology but will do "modifications".
However, as you may notice, Intel still lives in 20-years old paradigm of "synchronous" design. That is why many under-educated Intel bulls are trying to tell you that more than 100MHz is not doable. They are obviously infamiliar with modern "clock forwarding" technology which has been successfully used in DEC Alpha designs, where they have achieved record performance, both in integer and massive floating caclucations, as well as in network servers.
Take care,
Ali |
