The link above does not work but here is the articl. It was published in EETimes on 22 September 1997. You may find it on EETimes page by searching for Slot-1.
Good reading!
X86 vendors divided on Socket-7 strategies
By Ron Wilson
Austin, Texas - If Intel Corp. has its way, most, if not all, of next year's PCs will employ the company's proprietary Slot-1 as the one and only interface to a microprocessor. But PC makers say they are eager to extend the life of systems that use the older, slower Socket-7 connection and are seeking Slot-1 alternatives. And it looks for now like they will get at least two of them.
Both Advanced Micro Devices Inc. and Cyrix Corp. plan enhancements to Socket-7-type CPU interfaces for their next generation of desktop X86 microprocessors, the companies told EE Times last week. But they appear to be moving in different directions toward that end, raising the risk that the market next year will have to choose from among three distinct CPU interfaces.
"You can be sure there's a great deal of interest in extending the life of Socket-7, and OEMs would all request that fragmentation not happen in this area," said Tom Schmidt, a PC design engineer at Digital Equipment Corp. in Acton, Mass.
Both AMD and Cyrix have current products based on the Socket-7 interface used in the original Pentium CPU. Ironically, the Nexgen architecture on which the AMD chip is based had a non-compatible interface with a backside bus-a configuration not unlike Intel's Slot-1. But the market soundly rejected an interface that differed from that of the Pentium.
Indeed, when AMD bought Nexgen Microsystems and put its label on the Nexgen 686, one requirement was that the chip have an Intel-compatible interface.
Currently, both AMD and Cyrix claim to outperform a Slot-1-based Intel processor running at a similar clock frequency. "Our 6X86MX at 188 MHz will give better Winstone performance than a Pentium II 233 MHz, even though we are limited to a 75-MHz Socket-7 bus and the Pentium II has a 116-MHz backside cache bus," said Cyrix director of strategic planning, Darrell Benke.
But as AMD and Cyrix CPUs exceed 200-MHz clock rates, the existing, 66-MHz to 75-MHz Socket-7 interface threatens to become a serious bottleneck. Modifications must be made to Socket-7 if system performance is to continue its upward ramp. Intel has made it clear that it does not intend to license Slot-1, so for AMD and Cyrix, returning to Intel compatibility is not an option.
The problem with Socket-7 is that it is a shared bus, connecting the CPU to both the system-controller chip and the L2 cache. The sharing makes it difficult to increase the speed of the bus beyond its current 66 MHz to 75 MHz.
Consequently, L2-cache performance on Socket-7 severely lags behind the speed of L2 cache on the dedicated backside bus of Pentium Pro and Pentium II CPUs.
"Socket-7, as now defined, is a three-point bus," observed Atiq Raza, chief technology officer and vice president of AMD. "It connects to the CPU, the Northbridge [system-control] chip and the L2-cache system control
"In contrast, Intel moved the L2 cache to a backside bus on the Pentium II, so that everything in the Slot-1 interface is a point-to-point connection. That does make it easier to increase the frequency of the interface."
But that advantage does not necessarily make Slot-1 a faster interface. "For some reason, Intel chose to use more bus cycles to go to the Northbridge via Slot-1 than are required in Socket-7," Raza said. "That means that Slot-1 has to have a significantly higher clock rate than Socket-7 to achieve the same performance on Northbridge-intensive operations, like writing graphics data." Such operations-which become more critical with the Accelerated Graphics Port-may actually point up the value of Socket-7.
The dilemma
So the problem for AMD and Cyrix is how to open up the Socket-7 bottleneck without creating an interface so foreign that OEMs will not accept it. And they're pursuing divergent routes to that goal for their next generation of flagship CPUs.
AMD's approach appears to involve packaging. "If you remove the L2 cache from the bus, you can outperform Slot-1 with the Socket-7 interface," Raza said. "The crux of the problem for 1998 is how to move the L2 cache to a backside bus without leaving the Socket-7 mechanical spec.
"You can, for instance, design an L2 cache with a vertical pinout. That would make a low-profile mechanical assembly that would plug into a Socket-7 socket. And with the L2 cache on a separate bus, you can increase the frequency of the interface very significantly without abandoning LV TTL. That is particularly true if you help out the timing by using clock-forwarding techniques, similar to those used by Rambus."
Raza appears to be suggesting a CPU module that, like the Pentium Pro, would have an internal backside bus connecting to an L2 cache. The module pinout would be Socket-7-compatible. But transmitting the clock along the bus, with the data and control signals, instead of attempting to synchronize everything to an external master clock, would speed and simplify the timing.
Cyrix, for its part, has "been circulating a spec for a 100-MHz Socket-7 interface to some of our OEMs in Taiwan," Benke confirmed. The spec does not require a backside bus for the L2 cache, nor does it call for different electrical signaling levels. It does require integrating the L2 tag RAMs into the system-controller chip, and it mandates very close attention to setup-and-hold times.
Clocking would be the same as in the current Socket-7. "The spec requires careful board layout, but nothing impossible," Benke said.
He said the capability is there to extend the spec to 133 MHz. "But beyond about 100 MHz, you really have to look at reducing the signaling voltage-although the evolution of dual-data-rate SRAMs might be a model.
"At higher speeds, it might be worthwhile to look at SSTL, or perhaps HSTL. I don't think we would consider using GTL+, because of the possible intellectual-property issues with Intel."
Beyond '98
Both companies agree that even with extensions, Socket-7 will not be sufficient for the 1999 generation of CPUs.
"CPU performance will be so high that both Socket-7 and Slot-1 will be inadequate," Raza said. "At that point, we need a bus with 200- to 500-MHz speed, capable of comprehending intensive graphics transactions. We need multiple Gbytes/second. I think that at that point, we will definitely need to use clock-forwarding techniques, with separate transmit- and receive-signal lines, similar to Rambus. An example would be what Digital Equipment Corp. has done on the recent Alpha designs.
"This may or may not require a change in signal levels, but it would certainly be very difficult without clock forwarding."
If AMD in fact intends to follow in Digital's footsteps, it could be planning a very sophisticated bus indeed. The most recently described Alpha design uses a deeply pipelined L2-cache bus at HSTL-derived switching levels. The interface can maintain three cache transactions in the pipeline at once, and it gives the chip an L2 bandwidth of 4 Gbytes/s.
Cyrix appears to be at a much more preliminary stage in thinking about its next interface. But it appears to be leaving the door open to AMD.
"It is important that we and AMD are unified in building an infrastructure for the next interface," Benke said. "It only makes sense to work together."
He would not comment on whether Cyrix and AMD are cooperating on the specification currently in-process, but it appears that they are not.
Indeed, Raza appears willing to go it alone against Intel if necessary. "I don't believe it is necessary for us to license a bus or a mechanical assembly," he said. "I believe our customers will support both our approach and whatever Intel decides to do, so long as the AMD offering is attractive in price and performance.
"That has certainly been our experience with the MediaGX processor, which is not pin-compatible with any Intel product but has been very well received."
Copyright (c) 1997 CMP Media Inc. |
