Your claim that somehow this process tests the .18um ground rules harder than the equivalent .18um bulk process is ridiculous. I've seen multiple checking decks run against critical groundrules on numerous designs. The number of minimum ground rule occurances will be in the hundred of thousands if not millions. Why do you think these designs are smaller and run faster from generation to generation? Designers will generally use anything that is given to them. And I have seen and understand the actual design rules since I worked in the area prior to retirement. Also, why do you think they call them rules? In fact, very often, designers will ask for specific ground rule waivers for critical designs. And pleeeese, don't tell me it is different at Intel.
No, I never made any such claim. I merely pointed it out as a possibility. Without knowing both IBM and Intel's 0.18 micron design rules, and without having a layout for the Power4, Merced, and McKinley, it's impossible to evaluate the yield loss due to design complexity. In your initial argument you neglected it completely and seemed to demonstrate a lack of understanding regarding the issue. I merely sought to clarify. The bottom line is the more design rules you push or break, the more problems you're going to have fabbing the part... period.
It is common knowledge thu the industry that it costs approx $1500 to $2000 to process a wafer thu any roughly equivalent high performance 6-7 layer metal advanced CMOS process (not counting depreciation). If you think it is closer to $200 or $20,000, then it makes no sense for me to discuss this with you. So, $2k is a conservative estimate accounting for the xtra cost of an SOI substrate. IBM competes on a foundry basis and so must have competitive pricing for equivalent processes. They can get some premium for something proprietary like Si/Ge BiCMOS or SOI but it is not the norm.
I agree that the "norm" for per 8" wafer cost is ~$2K. However, as I pointed out IBM is an "art fab." SOI wafers cost extra, which would add $400-$600. I don't think SiGe is going to add much to the cost... you're essentially adding one additional layer to create the bipolar transistors. The overall cost would depend on whether you had to run it through the critical steppers or could use a longer wavelength one. Depending on how exotic the back-end is that may add a few dollars a wafer start as well. I'll ignore the $200 / $20K comment as it's obvious flame bait. I would not, however, be surprised if IBM's cost/wafer is closer to $3K than $2K for the reasons stated (assuming it's not running on a simple bulk process).
.....will the process and design wannabeees please read this article so we don't have to go thru all of this preliminary stuff again.
Given that you don't know for sure what the members of this forum do for a living... don't you think that statement is a bit presumptuous? |
