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Technology Stocks : Intel Corporation (INTC)
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To: pgerassi who wrote (144617)10/3/2001 11:32:52 AM
From: Tenchusatsu  Read Replies (1) of 186894
 
Pete, <This quote just proves my point, the operation is performed in 1.5 cycles of base frequency not 0.5 cycles.>

Here's a hint, Pete ... It's called P-I-P-E-L-I-N-I-N-G. After the first instruction is sent through, the second instruction is stuffed into the pipeline 0.5 cycles later. The latency is 1.5 cycles, but the total throughput is one instruction every 0.5 cycles, or two instructions every full cycle.

Let's repeat that word again, just in case you missed it ... Piiiiiiipeliiiiiiiiniiiiiiiing.

Not only that, but now you are no longer sticking to your "two pipelines 180-degree out-of-phase" argument? Gee, you change your story more often than the Taliban!

Tenchusatsu
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