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To: Noel who wrote (146679)11/2/2001 9:42:39 PM
From: maui_dude   of 186894
 
Noel,
Re : "What makes you think removing 5-10% of transistors will reduce the die size? Most designs are metal limited not transistor limited"

I made a rough assumption that 5-10% extra transistor resulted in proportionally percentage increase in the interconnects.

Re : "So moving from 0.18 micron Willamette to 0.13 micron Northwood will give a great cost benefit"

Then why is the cost benefit only 5% by end of 2002 ? Isn't most of .18 to .13 migration complete by then ?

Re : "I don't think there has ever been a 25% cost gain just from process transition."

For the same yield and die size(and assume 50% area increase due to the cache and new logic)? why should it not give you 25% cost gain from just the process shrink ?

Maui.
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