wbmw,
the test program can be improved if we add input, such as your about the Piii's ability to use simple decoder for some of the instructions in parallel.
As far as labeling, I would be for performance based labeling, based on some industry set standards. P4 has at least 4 clocks: FSB, the 1/2 clock used by trace cache, possibly decoder, possibly L2, nominal clock, used by complex integer, address lookups, (I don't know about FP), double clock used by ALU.
Which one occupies the largest real estate? If L2 and decode run at 1/2 speed, plus trace cache which does, they may constitute the majority of real estate on the chip. Either that, or the nominal clock. I don't know.
Joe |
