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Technology Stocks : Advanced Micro Devices - Moderated (AMD)
AMD 217.91+0.9%Dec 5 9:30 AM EST
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To: mas_ who wrote (156707)4/17/2005 11:08:21 PM
From: Elmer Phud of 275872
 
mas

you have to find out first whether anybody has a dirty cache version of a memory address, so yes it is sequential as IBM have described. If you have on-die memory controllers like Power 5 or Opteron then yes the requests are issued simultaneously but with Fsbs you are generally SOL.

Not so. When processor #1 issues a transaction to the memory controller every other agent on the bus sees it in real time. Any agent can issue a HIT# or HITM# if they have a fresh or modified copy of that memory location. If they are in the middle of an operation and can't respond immediately, they drop both HIT# and HITM# and that causes a snoop stall to give them more time. If someone other than the MC has the data that halts the memory operation and the agent with the current copy supplies the data. Any other agent which also needs to update that memory location, including the MC then "snarfs" it from the bus as it goes by.

I once developed the test capability for a chipset interfacing to the PPro FSB. There's obviously more to this than IBM is explaining. I don't know everything about the protocol and it's been quite a while since I looked at it in depth. Maybe I'm forgetting something?
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