I'm no expert but isn't SUN arch RISC? Doesn't this mean that each instruction does LESS than a comparable instruction on INtel's CISC arch? SO isn't the number of instructions per cycle also misleading are am I missing something?
thanks in advance, Claude
Claude, I am not expert either, since I got my EE degree five years ago and has been in the software industry since. But I think I can answer some of your questions.
SPARCs are indeed RISC. The main difference between CISC and RISC is in the hardware complexity. For RISC, the instructions sets are fixed in length, and there are a lot fewer of them than that in a CISC architecture. Both architectures use multiple pipelines, and in the case of Merced, they probably use up to 8 pipes. For RISC, each instruction takes the same number of clock cycle to complete, and less hardware complexity inside the ALU. What this also means is that they can amortize the savings they have in the ALU and to add more complexities to the caches, registers. That means they can potentially allocate a set of register banks per process, and thus greatly improves performance in processes context switch, etc.
Most of these processors nowadays are so complex now, they support branch prediction, branch forwarding, 3 level caches, huge translation look-aside buffers... I wouldn't care too much about the processor speed. There are a lot more than just processor speed. Things such as the number of levels of cache, I/O bus bandwidth, number of registers are very important too. Again, for different applications, I would evaluate how different architecture and OS fit. I wouldn't base much of my decision on simply clock speed. |
