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United States Patent 6,134,141
Wong Oct. 17, 2000
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Dynamic write process for high bandwidth multi-bit-per-cell and analog/multi-level non-volatile memories
Abstract
A write process and circuit for a non-volatile memory such as a multi-bit-per-cell Flash memory has multiple local memory arrays and a global bias circuit that charges row lines in the arrays for programming operations. A programming operation in an array includes a charging period during which the global bias circuit charges a selected row line to a voltage corresponding to a value to be written in a memory cell and a sequence of program cycles and verify cycles during which the selected row line is isolated to preserve the charge from the bias circuit. A global control circuit can use a capacitive coupling to the charged row line to raise and lower the row line voltage. In one embodiment, the row line voltage rises to a programming voltage to change the threshold voltage of the selected cell during program cycles and falls to a verify voltage during verify cycles to sense whether the selected cell has a target threshold voltage. Alternatively, the row line voltage remains constant as charged by the bias circuit if a maximum current for biasing a column line connected to a sense amplifier causes the programming voltage to be equal to the trip point of the sense amplifier when the memory cell has the target threshold voltage.
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Inventors: Wong; Sau-Ching (Hillsborough, CA).
Assignee: SanDisk Corporation (Sunnyvale, CA).
Appl. No.: 224,656
Filed: Dec. 31, 1998
Intl. Cl. : G11C 11/34
Current U.S. Cl.: 365/185.03; 365/185.22; 365/185.25
Field of Search: 365/185.03, 185.21, 185.23, 185.22, 185.25, 185.01
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References Cited | [Referenced By]
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U.S. Patent Documents
5,587,951 Dec., 1996 Jazayeri et al. 365/203
5,784,315 Jul., 1998 Itoh 365/185.22
Primary Examiner: Nelms; David
Assistant Examiner: Ho; Hoai V.
Attorney, Agent or Firm: Majestic, Parsons, Siebert & Hsue
17 Claims, 10 Drawing Figures |
