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Technology Stocks : Intel Corporation (INTC)

INTC 40.34

-2.6%

Dec 8 3:59 PM EST

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To: wanna_bmw who wrote (162489)	3/19/2002 8:53:24 AM
From: combjelly	Read Replies (1) of 186894

"Any reason why you think it would be 256KB?" Because it would be a very tight fit in 104mm^2. TBred is supposed to be 80mm^2, and there is no real reason to suspect that it will have more than 256k of L2 cache. So that leaves 24mm^2 for the memory controller (maybe 2-3mm^2), a 16 HTT channel for I/O (about the same), a 32 bit cHTT channel for SMP that is disabled in the first iteration (your guess of 5mm^2 sounds good). And that leaves 14mm^2 for all the other enhancements like the two additional stages, the changes made to enhance the bandwidth to the L2 cache and everything else. There just isn't any room for another 256k of L2 cache...

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