TWY, I have a question (or two):
You say that there is a spectrum of devices centered
at 60nm, and the Vt varies steeply along the spectrum.
Then you said that they need to shrink the process further
to fix the problem. Is not it true that after the shrink
the similar spectrum will occur but centered around,
say, 54nm, so the wings of distribution will go to even
smaller Leff, with ever smaller Vt, at this will
only alleviate the problem?
Also, you say the devices are typically 4um long, which
is a factor of 100:1 in geometry. Yet all pictures
usually show a single slice of that transistor. So,
the question how homogeneous the device might be along
the the channel? What about the edges of the channel?
Is there any leakage caveats there?
More, Intel presentations show structures called "halo
implants" which are intended to reduce the leakage,
specifically the leakage. In the same time the feature
size of this architectural element is 1/10 of the
gate Leff. Since the implant is a chemical kinetics
process happening in (turbulent?) atmosphere of
tool chamber, is not it reasonable to expect much higher
level of local fluctuations in the size and chemical
quality of this element, which may impact the leakage
adversely?
How about so-called "gate leakage" and possibility of
variety of fluctuational defects around it?
I am just making those obvious questions up. How they
are addressed in general manufacturing?
I feel somehow that the unfamous "red brick wall"
is much close than Intel's management wants us
to believe.
Regards,
- Ali |
