"PT, the 20MHz thing looks like a misprint. Maybe they meant 200MHz?"
A memory subsystem made up of DRAM can access a particular bit in a time on the order of 50 nsec. (Remember when SIMMS and DIMMS were 70 nsec, 70 nsec, etc., just a few years ago?). This is where he presumably got his 20 MHz figure from.
A 200 MHz access rate would be consistent with 5 nsec access times (from inside the DRAM, through the glue logic on the board, to the memory bus). Possible with SRAM, but pricey. (And the author mentions cache memory, separately, so he clearly was talking about main memory, not SRAM cache.)
Of course, an effective increase in bits per second retrieved is possible by accessing N bits at the same time. Access 50 bits each at 50 nsec and one has an effective GHz access rate. But nobody defines memory access this way.
There are lots of good reasons why DRAM cells and bit lines and all don't keep up in speed with SRAM cells and SRAM logic.
One of the reasons for VLIW/EPIC is to increase the effective memory parallelism by using very long instructions which can be worked on in pieces, so to speak.
--Tim May |
