Actually, what we have been working on is to package some of
the sub-unit pieces of the M6000, such as the multiplier and adders
and other small bits and pieces to salvage some value from the
effort made to design them. Larger pieces of the M6000 are so
architecture specific that they are of no interest to anyone. As
with the library, the actual circuits used for these offerings is
pretty much in the public domain. We have been able to use some of
the sram circuits that we co-own with ST for some designs, but
until we have a ram macro generator we will not make that a mainline
offering. Without the generator every design is hand honed, which
is impractical for cost/time reasons.
I think the M6000 business case is well detailed in the EDGAR filings:
no market research, no sales, no guarantee that the partner would
want the design when complete. Oversold and understaffed. Plus, the design itself just flat missed the window of opportunity. Right now we are confronted with a building huge surplus of X86 capacity, and while Intel is still very profitable AMD and NSM and IDTI certainly are not. Out of the engineers in the LA office who actually did the logic design all are gone. One circuit designer from LA is still with us.
To consider restaffing an effort is escaping reality. Unless we see
a way to get to the 500 Mhz - 700 Mhz clock speed it would be a waste
of money, and the design has no legs. We were stressed to make the
model run at 200 Mhz simulation environment.
Frank |
