Paul,
According to my research, patent number 4,972,338 (Memory management for microprocessor system) was issued on Nov. 20, 1990 to John H. Crawford; (Santa Clara, CA) and Paul S. Ries (San Jose, CA) and assigned to Intel. It was a continuation of (including streamline cont.) Ser. No.744,389, Jun. 13, 1985 which was abandoned (I am not sure precisely what this means).
The patent abstract reads:
"Microprocessor architecture for an address translation unit which provides two levels of cache memory management is described. Segmentation registers and an associated segmentation table in main memory provide a first level of memory management which includes attribute bits used for protection, priority, etc. A second page cache memory and an associated page directory and page table in main memory provide a second level of management with independent protection on a page level."
Is this the Crawford patent that you mentioned?
The patent was applied for on April 19, 1988, so it is unclear what the situation was for any licenses granted in 1987.
Anybody have any more information? |
