LSI Logic Introduces Synthesized ARM7TDMI(TM) Based Core With Configurable Size Cache
Based on the Popular ARM7TDMI, LSI Logic's Synthesized Core Provides More
Flexibility Than Fixed-Size Cache Processor Cores
MILPITAS, Calif., Sept. 21 /PRNewswire/ -- LSI Logic Corporation (NYSE: LSI) today announced the CW1008, an ARM7TDMI-based processor core complete with a unified cache memory configurable from 2 K bytes to 16 K bytes. The new core is available as part of LSI Logic's extensive CoreWare(R) library. The CW1008 is much more efficient and flexible than traditional fixed size cache processors.
LSI Logic's CW1008 core is fully synthesized for seamless integration with advanced ASIC design flows and has a four way set associative cache configurable to a 2 K, 4 K, 8 K, or 16 K byte size. By having multiple cache size options, the core provides efficient use of on-chip cache for a broad range of applications with widely varying memory subsystem requirements. The CW1008 can use a variety of LSI Logic's standard compiled ASIC memories for its cache. This additional flexibility allows the system level designer to trade off cache memory speed against power dissipation and die size requirements. The CW1008 embedded CPU core also includes a memory protection unit and write buffer.
"LSI Logic sees a growing trend toward more complex software programs requiring larger memory systems. On-chip cache provides the most effective way of maintaining high performance while minimizing chip area," said Bob Van Steenburgh, director of processor core marketing for LSI Logic. "The configurable nature of LSI Logic's ARM7TDMI-based cache provides further area optimization by providing a flexible cache which can be tailored to fit customers' system requirements."
The CW1008 is available now, implemented in LSI Logic's G11(TM) 0.25-micron process technology. The core runs at clock speeds of 70 MHz at 2.5V with power dissipation of 1.5 mW/MHz.
To assist customers in determining the optimal cache size for their particular application, LSI has also developed a CW1008 evaluation device with all four different cache sizes implemented onto one chip. The cache size is selectable via two hard-wired programming pins on the device. The CW1008 evaluation chip is packaged in a 208-pin PQFP and also available now, both as either a standalone device or mounted on a header card for use with the PID7T development board from ARM Ltd.
Peripherals, Reference Designs, and Silicon Development Platforms
LSI Logic's ARM cores are supported by a robust library of AMBA(TM) peripherals, proven reference designs, and a silicon development platform for easing the integration of complete CPU subsystems into complex system-level ASICs. LSI Logic also offers the very highest quality design support through its team of field CoreWare engineers who each specialize in the use and implementation of particular cores.
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