IMEC launches 100-nanometer process program
eetimes.com
By David Lammers
EE Times
(07/14/99, 9:16 p.m. EDT)
SAN FRANCISCO — IMEC (Leuven, Belgium), the microelectronics research center, will launch a major new program to integrate various 100-nanometer process technologies and will invite participation by U.S.-based semiconductor companies for the effort, the consortium announced at Semicon West.
The program will be aimed at having 100-nanometer process technology ready by the 2003 time frame, as called for by the International Semiconductor Technology Roadmap, said Gilbert Declerck, who became president of IMEC last month after the death of Roger Van Overstraeten from cancer.
IMEC (pronounced EE-mek) originally stood for the Interuniversity Microelectronics Center. But the center has grown to encompass a research agenda that rivals that of International Sematech (Austin, Texas). With a 1999 budget of $88 million, IMEC has a staff of about 850, including about 200 researchers who remain on the payrolls of the consortium's participating companies.
The goal is to take the results of IMEC's ongoing program to create a complete 193-nm wavelength lithography solution, and combine that with the other requisite technologies in a process-integration program lasting about three years.
"People want to have more process integration in this program," said Ludo Deferm, an associate vice president of IMEC. "The interactions are unpredictable among all of these new materials."
The 100-nm program already has the support of the four largest semiconductor vendors based in Europe, and from Europe's major equipment and materials vendors. Over the next six months, an additional coterie of U.S. semiconductor vendors, and a dozen or fewer equipment and materials vendors, will be recruited to join the program.
Participants will work to integrate copper interconnects, a low-k inter-metal dielectric with a k-value of 2.6 or less, and a high-k gate-insulation material. The project will create simple test circuits, and examine the interaction of the die with the chip-scale packaging that is commonly used for high-end logic devices.
U.S. companies have already participated in a number of IMEC programs. The 193-nm lithography integration program has about 50 people on site in Belgium, and fully half of those are U.S. citizens, said Johan Van Helleputte, an IMEC vice president.
But for the most part, U.S. device makers have worked in bilateral programs, typically where one device maker contracts for a research program of limited scope.
"We want to be open to U.S. participation," Deferm said. "That is a new thing for us, but why not? The mentality at IMEC has changed a lot over the past 10 years."
Integrating a high-k gate insulation material may prove to be a challenging part of the program. While much attention has been placed on copper interconnects, and on the challenge of finding a low-k material that can withstand the thermal and mechanical stresses in a process flow, the high-k challenge is equally daunting. Tantalium pentoxide, titanium oxide, and barium strontium titanate will each be considered, with an eye to how the materials perform as etching is applied to the poly gate layer.
Deferm said the goal is to find a gate-insulation material with a k value greater than 10, which can be applied at a thickness of less than 20 angstroms. For logic circuits, a key consideration is the impact of the gate insulator on the electron mobility at the channel. Silicon dioxide presented a good interface with the silicon, but new materials can cause the electrons to bounce around and slow the device performance.
Also, the 100-nanometer program will concentrate on more advanced etch techniques.
"To keep our etch profile and device dimensions within 100 angstroms requires better selective profiling control," Deferm said. "To do that without damage, so that the plasma charging does not damage the gate, is very challenging." |
