Advanced Micro vs Intel (AMD / INTC) Message Board

STOCKTALK

We've detected that you're using an ad content blocking browser plug-in or feature. Ads provide a critical source of revenue to the continued operation of Silicon Investor. We ask that you disable ad blocking while on Silicon Investor in the best interests of our community. If you are not using an ad blocker but are still receiving this message, make sure your browser's tracking protection is set to the 'standard' level.

Technology Stocks : Advanced Micro vs Intel (AMD / INTC)

Public Reply Prvt Reply Mark as Last Read File

Previous 10 Next 10 Previous Next

To: kpf who wrote (2439)	9/20/2007 11:57:06 PM
From: Elmer Phud	Read Replies (1) of 2596

Klaus Considering that the DD is really derived from actual yield numbers. DD is derived from defects. Now, _this_ is not difficult - as far as i see. How do you know there is a defect independent of test? Do you go over every square micron of each die layer by later with a electron microscope and hope you see one? Is that how you find defects? Without the ability to identify a defect there is no way to know if there is one. So tell us, how do you know if there is a defect other than by testing? They are visible. They just don't fail always. If they don't fail then how are they visible and to whom? They might work at a frequency out of spec. Then if you test to spec they won't work. I thought you said they don't always fail? Make up your mind. Do they work at spec or don't they? They might work at frequency within spec, but don't fit in a power envelope. If they don't fit within a power envelope then they're not in spec. You're contradicting yourself. Do they operate within spec or not? If you test for the power envelope then they will fail and fall within the DD number reported. You said they wouldn't. Which is it? They might work at frequencies and power within spec, but only for voltages out of spec. Etc.etc. Then if you test them within the voltage spec they'll fail and they'll fall within the DD number reported. So what's the problem? Test them to spec and the bad ones are killed off and the DD number properly reflects the true yield. It's really not that difficult a concept to grasp. A transistor has several dimensions which determine its behaviour. You can only fab it with tolerances of several nanometers, in many dimension. Couple nanometers plus or minus in gate-length or other dimensions change the behaviour in how fast it can switch, how much current goes through in on-state, how much leakage you have etc.etc. This was always so - it's just that you can't shrink the tolerances of manufacturing as fast as you can shrink transistor dimensions, so variation has already become the dominant cause of yield-loss - and it only can become worse going forward, even if you can compensate a good portion of it in DFM. So what? That's the long winded way of saying not all devices work to spec. You already said that about 3 times. So test to spec and toss the ones that fail in the garbage can. Why can't you do that? This is the point to start thinking from to understand nowadays manufacturing. The classical DD cases of shortcuts and broken wires are close to irrelevant for yields already. You have a very outdated understanding of yield reporting and how it is measured. All failure mechanisms should be screened out at sort, particle driven and parametric. The yield number is fed back into the model and reported as defect density, not because it is strictly particle based, but for historical reasons, the name is kept consistent. It is based on all failure modes. Final test should be assembly related defects only to a first order approximation. You are giving me some very interesting insights into AMD's problems. Please keep posting.

Report TOU Violation

Share This Post

Public Reply Prvt Reply Mark as Last Read File

Previous 10 Next 10 Previous Next