Could someone put this in the context of COHU:
Panelists at the FSA meeting also warned that testing was still a serious issue. Billat of
Robertson-Stephens pointed out that somewhere around the 130-nm node, the whole
nature of testing changed. "Our whole approach was based on the assumption-true so
far-that chip failures were dominated by defects," Billat explained. "But now it is
fabrication that dominates yield, not defect density. This will require us to forge a link
between design and test."
Keith Barnes, executive vice president of Credence Systems Corp.'s IMS Division,
brought late-breaking news of the half-full, half-empty variety from the testing front.
He said that the great hope for reducing test cost for digital circuits has been
extensive design-in of logic BIST coupled with use of BIST-aware testers. By
transferring most of the work of test vector generation and loading to the chip itself,
test engineers hoped to obviate critical speed paths across the probe head, reduce
tester memory requirements and, consequently, slash tester cost.
Barnes reported that the news was half good. "The first data is in now from design
teams that used the BIST approach," Barnes said. "The designers had estimated that
they would save an order of magnitude on the investment in test equipment, but at the
cost of getting only 40 percent of the throughput. Unfortunately, the order of
magnitude turned out to be right, but the throughput was only one-tenth of what they
had with conventional testers."
Full article: eet.com
TIA,
-PT |
