Hello Robert,
The PMAT news release is misleading. They say it self-planarizes
thus eliminating the need for CMP. First of all, I doubt they
are getting an "optically flat" surface across a whole wafer like
CMP gives. They probably see marginally flatter surfaces compared
to no planarization. Secondly, this doesn't account for vias. After
the insulator deposition, small contact cuts (vias) are etched into
the oxide to connect a metal layer to the one below it. The old
technology involved evaporating the metal directly over the contact
cuts. This leads to large dips over all the contact cuts. CMP gets
around this. Now, after etching the cuts in the silicon dioxide,
the holes are filled with tungsten plugs. after depositing the tungsten, the wafer is planarized, and the next metal layer is deposited. This is the key break through that allows more than three
metal layers. The virgin silicon dioxide was never planarized, the layer is planarized after the contact cuts have been plugged with tungsten. So a new oxide deposition system with a self-planarizing film does not get around the need for CMP. Look at the article and
note they qualify their CMP claims with "eliminates the need for
CMP on _some_ devices". I'd like to know which devices they're
talking about, I don't think it's high end CMOS.
Additionally, they have to contend with the difficulty of using a new insulator. There's no way they would use this for gate oxide. Which
means they have an interface problem between the gate-ox and the
layer between poly and the first metal layer. More importantly, how
does this oxide etch? The contact cuts that make the vias are smaller
than the wires, which are already really small. And there are millions of contact cuts on a chip. If they don't etch just as
precisely the state of the art silicon dioxide layers, then the
yield penalty would be overwhelming.
Uri Cummings
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