ASIC design is faster than designing a chip
from scratch, and design changes can be made more easily
Actually as designs change they can be reflected in new PLDs, and FPGAs very quickly. Some PLDs are EEPROM based and therefore can be reused and reprogrammed to reflect design changes. MOst FPGAs are reprogrammable too. For a quick time to market CSCO, ASND and others use FPGA extensively. They also use ASIC for high density designs and med to high volume products because ASICs require a NRE (non-recurring Engr charge up front from fab vendors); hence, ASICs cost more for low volume product. Of course, if high circuit density and PCB board space is the overiding factor, then ASIC is the only choice.
BTW, XLNX FPGAs are being used alomost exclusively at CSCO, ASND uses XLNX, ALTR, and others. This is meant as a tip. But you need to do more thorough research. I wish I had money to put in XLNX and ALTR when they were low in Dec. The big 5 NW also use PMCS, LEVL, .. ATM chip set. Sorry for the distraction. I could go on for days talking about FPGA, ASIC, PLD. |
