Patent on single chip codec system. Who is AVC Technology?..............
patents.ibm.com
5781788 : Full duplex single clip video codec
INVENTORS:
Woo; Beng-Yu, Los Altos Hills, CA
Li; Xiaoming, Yorktown Heights, NY
Hsiun; Vivian, Palo Alto, CA
ASSIGNEES:
AVC Technology, Inc., Cupertino, CA
ISSUED:
July 14, 1998
FILED:
Sep. 29, 1997
ABSTRACT: A single-chip video compression/decompression (video codec) chip is connected to receive a video input from a
NTSC-compatible or PAL-compatible camera and a transmit channel. Video information from the camera or other video
input source is compressed by the video codec and transmitted out in compressed form on a transmit channel. Concurrently,
compressed video information is input to the video codec from a receive channel, decompressed and output to the monitor or
other video output device, e.g., a television set. Only a separate single module of dynamic random access memory (DRAM) is
needed to provide storage for incoming and outgoing video data, compressed bit streams and reconstructed pictures for both
compression and decompression procedures. The compression of video information is by spatial decorrelation of the
intraframe information, and temporal decorrelation of the interframe information. The communication channel bit rate is further
reduced by quantization and variable length coding. Intraframe coding uses the redundancy of information within a single
frame. The processing is done on blocks of eight-by-eight pixels. Both the luminance and chrominance pixel blocks are
transform coded by a discrete cosine transform that changes the pixels from spatial domain to frequency domain.
EXEMPLARY CLAIM(s): Show all 12 claims
What is claimed is:
12. A video codec, comprising:
a single semiconductor chip providing for a video input connection from a camera and a video output connection to a
monitor of decompressed data, and a transmit channel and a receive channel of compressed data;
an interface connected to the chip for external connection to a separate frame memory dynamic random access memory
(DRAM) and provides for interim storage of incoming and outgoing video data;
a video compressor/decompressor disposed fully within the chip and connected to compress video information received
from said video input connection to be output on said transmit channel, and connected to decompress video information
received from said receive channel to be output on said video output connection;
wherein, said compression of video information is by spatial de-correlation of intraframe information, and temporal
decorrelation of interframe information, and said transmit and receive channels have communication channel bit rates
reduced by quantization and variable length coding;
wherein, the video compressor/decompressor includes decoding that is the opposite of encoding;
wherein a bit stream received on said receive channel is variable-length coded, and the length of each code-word is
determined, segmented and decoded;
wherein, a frame start, a group-of-block start and a macroblock start are used for triggers;
wherein, intra-type macroblocks are decoded using inverse zigzag, inverse quantizer and inverse discrete cosine
transform and sent out and stored in said frame memory DRAM;
wherein, inter-type macroblocks include a decoded motion vector used for motion-compensation of a macroblock in a
previous frame "t-1", and simultaneously the differences between "t" and "t-1" are decoded using inverse quantizer,
zigzag and discrete cosine transform;
and wherein, said decoded differences are added to a motion-compensated macroblock, to reconstruct a macroblock for a
current frame "t" and stored in said frame memory DRAM for reconstructing a next frame "t+1". |
