"What are your thoughts on AMD/Moto's decision to go with 2 additional metal layers in their .13mu SOI process (9 ML, as opposed to the current 7 ML)?"
The first thing to realize is that just because the process is capable of 9 ML does not mean that it will be used. And even if it is used, this does not imply that AMD will be using it. As you stated, the current process is capable of 7 ML, yet AMD only uses 6 ML. Perhaps Motorola is currently using 7 ML, and Motorola will be using 9 ML at 0.13-microns.
Others, who know more about this than I do, anticipate that AMD will not use 9 ML until at least the shrink to 0.10-micron. Others think that AMD will use more than 6 ML, possibly all 9 ML with the Hammer series only.
Additional ML do decrease yield for a given die size, but often shrink the die size enough that even percentage yield increases. For example, K7 was sampled at 5 ML, but produced at 6 ML. The reason for this was that the 5 ML die was 227mm2, while the 6 ML die was only 184mm2. Even with the extra metal layer, percentage yield was higher with the use of a higher number of metal layers.
K6-2 continued to use 0.25-micron design rules with metal interconnects, even when the device layers were shrunk to use 0.22-micron design rules. The reason for this is that shrinking the metal layers to 0.22-micron would have made them too thin. Although nobody seems to know, I would guess that K6-2/3+ uses six metal layers so that the metal layers can be etched using either 0.22-micron or 0.18-micron design rules. |
