IBM to produce logic and memory on single die
eet.com
...embedded DRAM brings advantages for image processing in a
digital camera, graphics processing in a notebook computer or data
processing in a networking system.
By David Lammers
EE Times
(12/12/98, 11:19 a.m. EDT)
SAN FRANCISCO — Claiming a major step forward for
systems-on-silicon, IBM Corp. vowed to take into manufacturing in 1999 a
process technology that marries its most advanced logic and memory
technologies on a single die. At the International Electron Devices Meeting
here, IBM reported on an effort to merge its trench-capacitor DRAM
technology with its next-generation logic at 0.18-micron design rules with
copper interconnects.
For IBM, the news amounts to pulling a fourth rabbit out of a hat. The
company already made waves with announcements this year that it is ready
to manufacture ICs with copper interconnects, on silicon-on-insulator (SOI)
wafers and with a silicon-germanium process.
Customers in the networking, disk-drive and digital consumer fields already
have expressed an interest in taking advantage of the on-chip bandwidth
possible with embedded DRAM. Adding DRAM to a logic process usually
compromises logic performance, but IBM's plan extracts virtually no speed
penalty for the logic. A separate presentation at IEDM detailed a
0.18-micron process with inverter delays of 11.9 picoseconds-one of the
fastest reported to date-with gate dimensions at less than 0.1 micron.
Embedded DRAM will be offered on that base logic process.
Gary Bronner, a DRAM technology manager at IBM, said the company's
decision to stick with a trench capacitor rather than the stacked capacitor
used by most other DRAM manufacturers allowed it to build a DRAM array
on the same die, with copper-interconnect technology.
Significantly, the scheme requires only five additional mask layers, which add
about 25 percent to the cost of the total process, said IBM researcher Scott
Crowder, who presented the IEDM paper on behalf of a much larger team
working at the company's semiconductor-development center in New York.
Crowder said the DRAM cell size of 0.6 micron is about 50 percent larger
than if IBM had used its optimized DRAM process, which yields a
0.4-micron DRAM cell size at the same process rules. IBM adapted its
256-Mbit DRAM technology, and will use that with a 0.18-micron logic
process that is still under development.
"There is about a one-generation penalty that you pay in terms of cell size
with embedded DRAM," Crowder said. "You have to come to this with the
right set of trade-offs [among cell size, cost adders and logic performance].
But if you try to add DRAM with the same cell size, in a logic process, it gets
much, much more difficult."
Small size
Despite the relaxed cell size, the 0.617-micron2 DRAM cell compares with a
4.2-micron2 cell size for an SRAM cell, which is among the smallest yet
reported, said Bronner.
The announcement here that IBM essentially has solved the problem of
embedded DRAM came in the final paper in the final session at the IEDM.
After Crowder's presentation, a dozen engineers-all from Japanese and
South Korean companies-questioned him and congratulated the IBM team on
its work.
What emerged from that post-session discussion was an acknowledgement
that the trench capacitor, used also by Toshiba Corp., and Siemens, is a
major advantage to embedding DRAM without compromising the logic.
NEC's approach
While NEC Corp., for example, has developed a "merged" process that
delivers a respectable logic performance exceeding 100 MHz, its use of a
stacked capacitor makes it difficult to match IBM's performance.
Key to that is retaining the ability to salicide the logic transistors after building
the memory array. Salicide-treating the logic transistors with a thin metal
layer (cobalt, in IBM's case)-is difficult with a stacked capacitor, said a
DRAM researcher from NEC. Fittingly, Crowder's father invented the
salicide process a generation ago at IBM.
IBM will take the process into manufacturing in 1999. The normal ASIC
design tools and libraries can be used.
Japanese and Korean DRAM vendors have been pursuing the embedded
DRAM vigorously, but with the exception of Toshiba, none has claimed that
DRAM can be added to its highest-performance logic processes.
To enable the salicide steps, IBM covered the wafer with nitride to protect
the memory-array areas, leaving them unaffected by the cobalt salicide. The
insulator was removed for the logic portions requiring the salicide steps, after
which the normal logic-process steps were applied. Use of the buried-strap
trench capacitor and bordered bit-line contact also means that the process
does not require additional high-temperature heat cycles.
A Hitachi engineer noted that finding customers willing to use embedded
DRAM can be a challenge. Many companies have been content to use
moderate-sized blocks of SRAM, which can be built without additional mask
layers.
However, embedded DRAM brings advantages for image processing in a
digital camera, graphics processing in a notebook computer or data
processing in a networking system.
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