AMD's New Muscle Puts Heat On Intel
By Robert Ristelhueber
The gang that couldn't shoot straight might be starting to make Intel
sweat.
During a panel session at last week's Microprocessor Forum, a
representative of the world's mightiest microprocessor maker found
himself on the defensive, insisting that his company's next chip would
keep up with Advanced Micro Device's upcoming K7 device. "I
believe we have a competitive product," said Srinivas Raman,
manager of Intel's microprocessor architecture and validation groups.
Even the notion of such a scene would have been absurd only a year
ago. AMD had once again stumbled, shooting itself in the foot by
failing to achieve adequate yields with its K6 processor. Memories of
the company's K5 debacle were still fresh in industry minds. Intel was
at the height of its power and prosperity, and AMD couldn't seem to
lay a glove on its arch-rival.
Yet last week, moderator Michael Slater questioned whether Intel
had the right stuff. "In looking at the K7, it appears to be in some
ways a more complex and sophisticated micro-architecture than the
P6," Mr. Slater said, questioning why Intel was relying on tweaks of
its P6 architecture with the upcoming Katmai instead of redesigning
the micro-architecture this year as AMD has done. Mr. Raman simply
replied that the Katmai/Tanner extensions would be up to the
challenge.
To be sure, Intel still dwarfs AMD in market share, revenues and
profits, and nobody expects that to change any time soon. But the
past year has seen the emergence of a significantly more confident and
competitive AMD. For the first time in recent memory, it is turning out
original designs that are equal to, and in some cases superior to those
of Intel, despite Intel's massive advantage in engineering depth.
For OEMs, this is providing more options but also more
complications. Because of the resurgence of AMD, and new parts
from Cyrix, IDT and Rise Technology, computer makers are going to
have to juggle inventory to accommodate the new choices, from
chipsets to printed circuit boards. But Intel's death grip, dictating what
technology OEMs would use, appears to be loosening.
Early this year, AMD apparently caught Intel off-guard in the low-end
of the PC market, taking a sizable chunk of that emerging segment.
Then, it took the initiative by convincing Cyrix and IDT to drop their
competing technologies and line up behind AMD's 3DNow. Intel is
still playing catch-up there.
The K7, described at length at the Forum, is AMD's first serious
attempt to compete with Intel at the high-end. Scheduled for
introduction in the first half of next year, the chip is said to run at
500MHz in a 0.25-micron process. It will be transitioned to
0.18-micron in the second half of the year.
Dirk Meyer, director of engineering for the K7, claimed at the panel
that the chip will outperform Katmai even when both are running at
500MHz. That allegedly will be accomplished by features including a
superscalar pipeline, large on-chip L1 cache, and the 200MHz EV6
Alpha bus interface.
"The K7 could be a real comer, especially using the Alpha bus,"
commented Nathan Brookwood, principal at Insight 64, based in
Saratoga, Calif. "It will have multiprocessor capabilities that AMD has
ignored before.
"The AMD we're seeing today is far different than the one we saw
three years ago," he added. "In my book, the entire difference results
from their acquisition of NexGen. Before that, they had very limited
capabilities to innovate in microprocessor design. They were just
following in Intel's wake, grabbing the leftovers Intel didn't want.
"In NexGen, they got a core group that understands complex
microprocessor design, with a sophisticated methodology for doing
that. And they have augmented that technical capability with much
stronger marketing," Mr. Brookwood said.
Marketing Game
But big hurdles remain, said Mike Feibus, principal with Mercury
Research, Scottsdale, Ariz. "I don't think anybody disputes that K7
looks pretty good technically speaking. The issue is, can they talk
their way into a segment that historically has been Intel only.
Ultimately, it's a marketing game. A lot of great processors have eaten
the dust of less-capable Intel processors."
Those other processors lacked compatibility with Intel, however, and
Mr. Feibus noted that Intel seems to be in no hurry to upgrade its P6
architecture to compete with K7. "They are basically going to ride the
P6 core for the next two years," he said..
AMD's many stumbles have made some observers skeptical about
their promises. "We'll see if AMD has gotten its manufacturing
problems squared away. It always comes down to whether you can
build it," said Tony Massimini, chief of technology for Semico
Research, Phoenix. "Theoretically, they could probably keep pace
with Intel, but what will they do in mid-2000 when Intel has the
Merced running at 0.18?" Others suggest, though, that the 64-bit
Merced is aiming at a higher-performance segment than the K7,
which will be marketed to desktop PCs as well as workstations and
servers.
AMD will need to build an infrastructure of third parties to support
K7 with chipsets and circuit boards, something it's managed to do
with its K6 processor. The company will also have to persuade
OEMs to handle yet another processor connection for K7, in addition
to the existing Slot 1 and Socket 7, and the forthcoming Socket 370
for Intel's Celeron chip. The K7 will use what AMD calls Slot A,
which has the physical characteristics of Slot 1 but different electrical
specs requiring a unique circuit board.
Specs disclosed
The K7 will feature three parallel X86 instruction decoders, a 9-issue
superscalar microarchitecture, dynamic scheduling with speculative,
out-of-order execution, and 2048-entry branch prediction table,
AMD said. It also will include 64K of I-cache and 64K of D-cache.
Other features including two general-purpose 64-bit load/store ports
into D-cache, a high-speed 64-bit backside L2 cache controller, and
deep internal buffering to support pipelines and external interfaces.
The Katmai/Tanner architecture from Intel will include the dynamic
execution and MMX technology of existing Pentium II processors, in
addition to streaming memory instructions, concurrent SIMD-FP
architecture, and new media instructions. As announced earlier, it will
be available in the first half of next year.
Intel said the architecture has packed add and multiply on different
ports to boost the floating point performance, and early prefetch
completion signaling to decouple data fetch from computation. It also
features a 20 percent improvement in write combining bus bandwidth
by enhancing system logic and processor interaction.
Other contenders disclosed their X86 designs at the Forum. Cyrix
discussed its Jalapeno core, a dual-issue X86 with register renaming
and out-of-order execution. It features a deep pipeline, with 11 stages
fetch to integer completion. It is expected to reach over 600MHz
when produced in 0.18-micron.
Jalapeno's integer units are fully pipelined, with parallel execution of
integer ops with integer multiplies and divides. The device also
features a single load/store unit, and a 256K 8-way associative,
8-way interleaved cache. The first Jalapeno device, the M3, will be
sampled in the fourth quarter of next year.
IDT's WinChip 4 uses two branch predictions, and executes
instructions in-order . The design includes a 128K L1 cache. It will
run at 500MHz in 0.25-micron technology, to be upgraded to
0.18-micron next year.
The micro-architecture includes an 11-stage pipeline, with pipelined
caches. Designed for Socket 7, the part is slated for production in the
second half of next year.
Newcomer Rise Technology said its mP6 family will use a three-way
superscalar architecture with six-stage pipelines. The low-power
technologies include the use of standard techniques such as system
management mode (SMM) , stop grant state, auto half powerdown
state, and stop clock state.
Rise said it executes three MMX multimedia instructions in every
cycle. It will use a 100MHz Supersocket 7 bus and includes 15 K of
L1cache memory. First production shipments are slated for this
quarter. |
