jim kelley, <From Samsung:
usa.samsungsemi.com
Argue with this whitepaper...you have been peddling nonsense. It will be noted on your next review. <G>>
If you have no clue, do not talk. The article
tries to deceive you and alike.
First, they are talking about a single RDRAM
chip. In a real system the chips are programmed
with additional delays to compensate for
propagation time to the farthest device,
or typically additional with 5-6.25 ns,
read Paul DeMone clear explanations as why.
BTW, this programmability is exactly the
important patened feature the Rambus is so
praud of.
Second, I am not aware of SDRAMs suffering
"from what is known as the two-cycle
addressing problem."
Look at the God-written document,
ftp://download.intel.com/design/chipsets/memory/pc133sdram/spec/sdram133.pdf
and you will find no requirements for two-cycle
RAS. Actually, if you want to compensate for heavy
load and weak drivers, you always have extra two
full clocks of precharge time to drive address
lines ahead of the RAS strobe, or exactly how
it is done in Intel chips. Therefore the actual
timing requirements are fairly relaxing in the
reality, and that's why it works in contrast with
unthinkably and unreasonably squeezed Rambus
interface.
Third, they compare best case RDRAMs with PC100 Cas2
and PC133 Cas-3 memory. Today there is plenty of
SDRAMS at 133 and 143MHz with true 2-2-2 timing.
Looks like Samgung wants to sell the slow-going
product and wants to grease sales with blatant
marketing.
Have nice trading,
- Ali |
