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To: Carter Patterson who wrote (43181)12/26/1997 7:22:00 PM
From: Paul Engel   of 186894
 
Carter - Re: "...Japanese in chip design (I think Fujitsu). Apparently
within 4 years, the line width will increase from 400 ..."

This entire thing is blown out of proportion.

Fujitsu announced a POTENTIAL technique for solving only ONE problem for only one type of device (p-Channel MOS) that has to be faced in getting to sub 0.1 micron features.

Fujitsu discussed some promising work using VERY SHALLOW implants of Boron using clusters of B10H14 ions. These heavy clusters, when implanted into n-type silicon create very shallow, abrupt dopant areas that tend to eliminate short-channel effects on P-channel transistors when defined using Direct Write Electron BEAM lithography with a gate length of about 0.05 micron.

The shallow/abrupt junctions alleviate what is known as the short-channel effect of an MOS transistor - the interference by drain depletion widths below the adjacent MOS gate device, artificially altering the ability of the MOS transistor to operate as a pure MOS device - with a well defined threshold voltage, low pre-threshold conduction/leakage currents, etc.

These were individual transistors - not CPUs nor any kind of integrated circuits.

They are attempting to get a consortium of companies to develop PRODUCTION equipment aimed at these clustered ion implant steps.
They are targeting a 3 or 4 years just to develop this ONE PIECE of ion implant equipment.

This represents 1 of about 1475 critical process steps that must be developed to get to sub 0.1 micron minimum feature size devices.

Paul
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