Lithography hit by R&D gap, downturn
Mark LaPedus
(03/04/2009 4:18 PM EST)
URL: eetimes.com
SAN JOSE, Calif. -- It was a triple-whammy for lithographers at the SPIE Advanced Lithography conference here last week, as the industry continues to be plagued by an R&D gap, technology delays, and, of course, the lousy economy.
Experts at SPIE warned about an alarming R&D funding shortfall for the various next-generation lithography (NGL) technologies--extreme ultraviolet (EUV), maskless and nano-imprint--creating more fear, uncertainty and doubt about the insertion of these schemes for mass IC production.
Some technologies like EUV remain delayed or on the ropes, leaving leading-edge chip makers to resort to an assortment of complex, costly and unpopular double-patterning schemes. And not only were there the usual and nagging issues with double patterning and NGLs, but the current and steep IC recession turned SPIE into gloomy event.
Business is simply terrible for the lithography and fab tool communities, causing some concern among analysts about the condition of the industry. Looking at the glass half full, the downturn could slow the roadmaps of various IC makers, giving the various NGL technologies time to develop and play catch-up with their promised timetables.
On the other hand, R&D budgets, and possibly key staffers, are being cut. During the downturn, some wonder if will there be enough R&D dollars to go around in order to finish a raft of incomplete NGL technologies.
Others also wonder which fab tool companies will survive the downturn. ASML, Canon and Nikon will likely survive, but many of the small, innovative NGL startups could fall by the wayside.
And in the short term, orders are drying up for lithography vendors. Worldwide lithography shipments are expected to drop from 544 systems in 2007, to 323 in 2008, to 184 in 2009, according to Nikon Corp., citing data from Gartner Inc.
Most believe the figure is too high for 2009, saying the industry is seeing the worst downturn in the history of semiconductor equipment. One industry source believes that lithography shipments could fall as low as 80 or so units in 2009, a staggering drop over 2008.
Some vendors are praying for a second-half rebound, but others aren't so sure. Frankly, the entire fab tool community is still ''looking for the bottom'' of the current downturn, said Risto Puhakka, president of VLSI Research Inc.
Regarding a common theme in lithography, Puhakka said there's an ongoing trend in the business: It's the word ''tomorrow.'' Vendors continue to make various claims about NGL, but they say the technology isn't ready today and promise to deliver ''tomorrow,'' he said. ''It's always tomorrow,'' he added.
Supporters of EUV, maskless and nano-imprint disagree with those assessments, saying they will be ready for the 22- or 16-nm nodes. Until then, leading-edge chip makers must resort to double patterning. At present, leading-edge chip makers are using 193-nm immersion technology for 45-nm chip production. Some are also using a combination of OPC, phase-shift masks and double-patterning.
Amazingly, optical lithography continues to defy the law of physics. 193-nm immersion can be extended to the 15-nm node (22-nm half-pitch logic), thanks in part to double patterning, said Burn Lin, senior director of the micropatterning division at Taiwan Semiconductor Manufacturing Co. Ltd. (TSMC). Lin is considered the innovator behind immersion, it was noted.
In doubling patterning, an IC maker is essentially doubling the process steps and creating two masks, thereby boosting production costs. There are also various flavors of doubling pattering: LLE, LELE, spacer and others.
Litho-litho-etch (LLE) may be cheaper than the rival litho-etch-litho-etch (LELE) method, but LLE uses newfangled processes that are somewhat unproven. LLE uses two lithography exposures and two resist layers to create smaller IC features. In comparison, LELE uses two lithography exposures and hard-mask etches to create smaller features.
A third method is called spacer or self-aligned double patterning. ''Spacer is a double patterning technique that uses deposition, anisotropic (directional) etching and trimming to produce smaller features on chips,'' according to ASML Holding NV.
Leading-edge chip makers may use one or more types of schemes, depending on the product type. So far, the most desirable technology is LLE, due to fewer process steps and cost.
TSMC's Lin said he prefers LLE, ''because of cost.'' The NAND flash crowd, which is said to be leading the process technology race, is already deploying some form of a double patterning scheme, reportedly spacer or sometimes called self-aligned double patterning.
The DRAM community, which is lagging in process technology, is evaluating spacer and LELE, analysts said. On the processor side, it appears none of the candidates are terribly attractive due to cost and complexity.
LELE ''is expensive,'' said Jongwook Kye, principal member of the technical staff at Advanced Micro Devices Inc. For spacer, ''Applied (Materials Inc.) has some solutions, but it's not perfect. Spacer is great for very regular designs.''
After double-patterning, it's unclear which technology will prevail. Some are pushing EUV, which uses 13.5-nm wavelength technology. As reported, EUV lithography has been dogged by delays due to the lack of sources, resists and masks. EUV is now being targeted for the 16-nm node.
EUV remains in question. ''Last year, (EUV) was a question of 'when.' This year, it's more of a question of 'if,' '' said Milind Weling, engineering director of signoff and silicon optimization for Cadence Design Systems Inc.
At SPIE, Intel Corp., one of the big backers of EUV, warned about an R&D funding gap for EUV inspection gear. In other words, the chip giant said the inspection community--such as Applied, Hitachi, KLA-Tencor and others--need to step up and put more resources into EUV.
Some complain that there has been an inordinate amount of funding directed at EUV, with little or nothing to show for it. Others say they will step up to the plate--if or when EUV is ready.
''I think there are a lot of questions about EUV,'' said Brian Trafas, chief marketing officer at metrology giant KLA-Tencor Corp. ''If the industry is ready for EUV, we'll be ready when the time comes.''
But what about the other pieces of puzzle? Many of the pieces are falling in place, but some wonder if they are too late. A prolonged downturn could delay many of the key elements of the EUV infrastructure.
Others wonder what's taking so long to develop the key technologies. It was only last week when chip-making consortium Sematech announced that it has entered into a joint development partnership to accelerate EUV mask blank commercialization with Asahi Glass Co. of Japan. Sematech also only recently signed a letter of intent with Japan's Tokyo Ohka Kogyo Co. Ltd. (TOK) to devise much-needed resists for EUV.
Perhaps the ongoing and nagging question is the power source. Cymer and others are devising EUV power sources. EUV vendors need 180 Watts or more of sustained power sources to enable IC production. But current sources have ''not met our specifications'' and still need a 20-to-30x improvement for production requirements, said Takaharu Miura, general manager for the 2nd Development Department Headquarters for Nikon.
Giving his observation of EUV, TSMC's Lin contends that the technology is still too expensive, lacks maturity and remains complex. Some estimated that an EUV tool today would run $90 million or more.
Maskless lithography is the ''most desirable'' NGL technology, because it is simple and does not require a photomask, Lin said. For years, chip makers have been using direct-write e-beam technology for use in processing select products, mainly ASICs and compound devices.
But today's e-beams are too slow in terms of throughput. So, the next step is to devise next-generation tools that make use of multiple beams, thereby increasing throughput.
TSMC is a strong backer of maskless for mass IC production and has invested in one developer, Mapper Lithography NV. But maskless remains immature, lacks the necessary infrastructure and is underfunded, Lin warned.
Many of the proposed tools utilize multiple beams to pattern a wafer, but it's difficult to control the light in these systems. If and when these tools are ready, maskless technology could find a home in more ''niche applications,'' said David Lam, principal of the David Lam Group, an investment and advisory firm for high-tech companies.
One of Lam's portfolio companies is Multibeam Systems Inc., a developer of maskless technology. Thanks to Multibeam, Japanese equipment giant Tokyo Electron Ltd. (TEL) is quietly making an entry into the maskless lithography business.
TEL will become the systems integrator for Multibeam's technology. TEL will market and sell a tool based on Multibeam's technology. TEL will provide the wafer handling gear, stages and systems. Multibeam will provide the engine and multi-beam technology.
Beyond maskless and EUV, the real darkhorse is nano-imprint, which resembles a hot embossing process. During a panel discussion at SPIE, Lin listed the current status of the various NGLs. He intentionally excluded nano-imprint from the list, because he does not consider it a contender for IC production.
The nano-imprint crowd disagrees, claiming the technology has already demonstrated sub-10-nm resolution. Over time, there could be a shift towards nano-imprint for use in the production in next-generation memory devices, such as crossbar technology, said Mark Melliar-Smith, chief executive of Molecular Imprints Inc. (MII), a developer of nano-imprint tools.
At SPIE, Hewlett-Packard Co. claimed to use nano-imprint in the development of the memristor, the fourth passive circuit element after resistors, capacitors and inductors. Invented in 1971, this "memory resistor" represents a potential revolution in electronic-circuit theory akin to the invention of the transistor -- and perhaps its time has finally come. But as with that earlier device, it will take a killer application to get it off the ground.
Another opportunity for HP, MII and others is within the disk drive industry. Nano-imprint could enable the development of disk drives based on next-generation ''patterned media'' technology, Melliar-Smith said.
Based on the trends, NGL needs more funding. Cadance's Weling offered a new solution to the problem: a bailout. ''Lithography is in need of a stimulus package,'' he said. |
