MIPS Technologies, Inc. Announces New MIPS32 4Km Processor Core To Reduce the Cost of Networking, Voice Over IP, DVD, xDSL and Cable Modem Applications
MOUNTAIN VIEW, Calif.--(BUSINESS WIRE)--Sept. 20, 1999--
Configurable 1.4 mm2 Core Includes Robust 32-bit
Internal Architecture and Optimized Instructions
That Provide High Performance At Low Cost
MIPS Technologies, Inc. (NASDAQ:MIPS) today announced the immediate availability of the MIPS32(TM) 4Km(TM) processor core that provides highly-tuned embedded application specific instructions in a very compact and low cost implementation. A new implementation of the MIPS32 architecture, the MIPS32 4Km processor core is designed for embedded applications that require a powerful general purpose 32-bit processor. It will greatly reduce the cost to implement applications such as networking, Voice Over IP (VOIP), xDSL and cable modems, and digital consumer products including handheld devices, digital TVs, DVD players, digital cameras and camcorders.
"New systems must be cost-effective to meet market requirements," says Jayan Ramankutty, VP Engineering, Lara Technology. "The new MIPS 32 4Km processor that is used in Lara's MediaExpress Processor (MxP)(TM) is an excellent solution because of the small core size, powerful instruction set and configurable features." MxP(TM) is the media streaming processor used in Lara's Unified Services Exchange(TM); a carrier class VoIP switch that was awarded "Best of Show '99" at Networld+Interop 1999 in Atlanta last week.
In addition to its robust MIPS32(TM) architecture-compatible 32-bit general purpose processor, the MIPS32 4Km includes specially optimized instructions including single-cycle 32x16 multiply and accumulate instructions, count leading zeros and ones, conditional data moves, and data cache prefetch instructions.
A second key benefit is that, as with all MIPS32 4K(TM) processor cores, it can be easily configured to meet the precise price/performance considerations of each application. This allows an SOC designer to implement application-optimized cache and memory access control logic blocks. Since memory, and especially high speed cache memory, has a significant impact on overall silicon cost, this allows the designer to configure the new processor core to meet the exact needs of the application while incurring the minimum silicon cost. Because the new processor core is provided as a "soft" or synthesizable core, it is portable to any 0.25, 0.18 micron, or future submicron CMOS manufacturing process.
"The MIPS Technologies approach of providing flexible cores that can be tailored to specific applications matches up well with the needs of our customers," said Ana Hunter, vice president of worldwide EDA Services at Chartered Semiconductor Manufacturing. "We can provide cost-effective, high-performance cores for systems solutions because customers select only the features they want. By selecting MIPS Technologies' cores from Chartered, customers acquire intellectual property that has been proven in silicon with Chartered libraries and our advanced submicron process technologies."
"With our wide range of RISC processor cores," notes Lavi Lev, senior vice president of engineering at MIPS Technologies, Inc. "we are well-positioned to meet both the low end and high end requirements, of our targeted applications. This high performance 32-bit general purpose processor architecture allows SoC designers to achieve new levels of performance at an unheard of price. One of the advantages of the MIPS(R) processor architecture is that a natural upgrade path exists for applications that need even greater levels of performance. For example, applications can be scaled to 64-bit functionality and of course, for those applications that need DSP capabilities, our licensees such as Texas Instruments can provide single-chip solutions that offer both units in a single ASIC."
Texas Instruments is the lead licensee for the MIPS32(TM) 4Kc(TM), MIPS32(TM) 4Km(TM), MIPS32(TM) 4Kp(TM) and MIPS64(TM) 5Kc(TM) cores and is integrating them together with its world-leading DSP technology on the same chip to provide high levels of DSP performance coupled with the strengths of the MIPS processor. This will increase the already extensive reach of the MIPS(R) architecture into an even wider range of applications in networking, communications, digital consumer and embedded markets.
The new synthesizable MIPS32 4Km core implements single-cycle MAC instructions. The MDU (Multiply Divide Unit) enables 16-bit x 32-bit MAC or multiply and accumulate instructions to be issued every clock cycle. Thus a full 32-bit x 32-bit MAC instruction can be issued every 2 cycles. The MIPS32 4Km is capable of 200 million MAC/s at 200 MHz (worst case frequency in a 0.18 um process). In addition to the single-cycle MAC, many of the MIPS32 4Km features, such as the 32-bit arithmetic unit, large register file (32 general-purpose 32-bit registers) and 4-way set-associative cache controller, are optimized for embedded systems. As a result, implementing a V.34 32.6Kbit/s modem in software uses less than 25% of the processor power at 200 MHz. The MIPS32 4Km core supports powerful MIPS32 instructions like conditional data move instructions for predicted execution and data cache prefetch instructions for data streaming.
The MIPS32 4Km is a member of MIPS Technologies roadmap of processor cores that range from low-cost 32-bit processor cores, to higher performance 32- and 64- bit processor cores, up to very high performance (1000 MIPS and up) 64-bit processor cores with 3D graphics extensions.
The MIPS32 4Km is available in easily synthesized electronic file formats. It includes a five-stage instruction pipeline optimized for system-on-chip or SOC implementations, 32 general purpose 32-bit registers, four execution units, power management features, a programmable cache memory controller and block address translation unit or BAT, and a single clock-based and fully static design. These features make the MIPS32 4Km ideal for integration into a wide range of SOCs using any standard 0.25 or 0.18 micron CMOS process technology. Using 0.18 micron geometries, the MIPS32 4Km(TM) can be implemented in as little as 1.4 mm2 in die size and uses as little as 0.5 mW/MHz.
The MIPS32 4Km is delivered as a synthesizable RTL files with a full complement of support tools and development software. These include installation and configuration tools, synthesis, scan and ATPG (automatic test program generation) scripts, support for numerous libraries and memories, BIST and floorplan design support, pre- and post-layout timing analysis scripts, simulation and verification tools, functional models and test chip specifications and implementer guides. In addition, the MIPS architecture is one of the most widely supported of all processor architectures with over 60 tool vendors and 170 development products available from third party development tool suppliers.
About MIPS Technologies, Inc.
MIPS Technologies, Inc. is the world's primary architect of embedded 32-and 64-bit RISC processors. The company drives the broadest architectural alliance that is delivering 32- and 64-bit embedded RISC solutions. It offers the only embedded 64-bit RISC architecture for emerging digital consumer, network systems, and information management applications. The company licenses its intellectual property to semiconductor manufacturing companies, ASIC developers, and system OEMs. MIPS Technologies, Inc. and its licensees offer the widest range of robust, scalable processors in standard, custom, semi-custom and application-specific products. Developers can choose from a broad menu of price/performance options that include execution units, clock speeds, instruction widths (16-, 32- or 64-bit), cache sizes, memory bandwidths, memory protection schemes, system interfaces, and on-chip system logic.
Licensees currently include: Alchemy; ATI Technologies; Broadcom Corporation; CommQuest (IBM); Integrated Device Technology, Inc. (IDT); Lara Technology, Inc.; LSI Logic Corporation; Macronix; NEC Corporation; NKK Corporation; Philips Semiconductors; Quantum Effect Devices (QED); Sony Corporation; SiByte, Inc.; Synova; Texas Instruments Incorporated and Toshiba Corporation. Numerous companies utilize MIPS-based(TM) intellectual property. MIPS Technologies, Inc. is based in Mountain View, California, and can be reached at 650-567-5000 or mips.com
MIPS is a registered trademark of MIPS Technologies, Inc. All other trademarks are the property of their respective companies. All press materials are available on the World Wide Web via: mips.com.
CONTACT:
MIPS Technologies, Inc.
Constance Sweeney, 650/567-5059
cks@mips.com
or
Brodeur Porter Novelli
Mark Ferrone, 408/324-4848
mferrone@brodeur.com
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