Hi richard suckla; Re the conversion from EDO to SDRAM. It is true that, at the time that designers designed the first major SDRAM systems, EDO was cheaper than SDRAM. But that doesn't matter too much, what matters is what the prices will be later on.
As far as designing new mousetraps when the old ones will do, you got me. I have no idea why companies hire design engineers to whip out new designs. Must have something to do with trying to keep up with the competitors or something like that. Me, I just do what I'm told and try to have a good time.
Anyway, the thing to remember is that designers do not design around current pricing. Instead, since their products end up being manufactured in the future, they design around future prices. So when it became clear that SDRAM would not carry a price premium to EDO, designers gave it more consideration.
It also turns out that SDRAM is much, much, much easier to use than DRAM. DRAM has huge numbers of bizarre timing requirements. SDRAM is simplicity itself, with only about five significant requirements. So designers put SDRAM into new designs without any hesitation. Getting a design done faster is good for time to market. Plus, people just like to do things the easy way. Here is a link to some old EE-Times articles showing SDRAM getting cheap:
Samsung grabs for 64-Mbit DRAM lead December 11, 1995
"We are going to be absolutely up-front about the premium for SDRAM over EDO DRAM," Ellsberry asserted. "Right now, SDRAMs are selling at about a 25-percent premium over similarly organized EDO parts. In the first half of 1996, we will drop that figure to 16 percent, then 8 percent in the second half. In the first half of 1997, there will be no premium for SDRAM."
techweb.com
When a designer sees an announcement of no premium for an easier to use product (that also had considerably higher bandwidth per part, though not necessarily higher bandwidth per system), they jump all over it. The problems with RDRAM is that it is not cheaper, doesn't have much of a hope of getting cheaper, and is extremely difficult to design in. DDR is cheap and easy, and that is what makes the best parts. (Dates too.)
-- Carl
P.S. Technical note on the timing requirements of SDRAM, and why they are so simple. The significant ones are setup and hold times, clock high and low times, and clock to output prop delay min and max. The other timing stuff consists of cycle counts (like CL2 or CL3), and is trivial. The worst memory architecture ever, from the point of view of difficulty in design, was VRAM, which had well over 100 significant timing requirements. It would take a good guy days to check the timing numbers for a VRAM based memory system, and he was typically a little loopy forever afterwards... |
