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Politics : Formerly About Advanced Micro Devices
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To: Scumbria who wrote (49545)2/14/1999 11:26:00 PM
From: Tenchusatsu   of 1581819
 
<However, in the real world of x86 code, the likelihood of having >4 consecutive instructions with no hazards is close to zero.>

That's my feeling as well. The guys who really know the P6 core's traffic patterns aren't talking. My feeling is that P6 processors can achieve more than three or four outstanding memory accesses at a time. How often it actually gets above three is a mystery to me. Like Ali said, the x86 architecture is, er, "challenging" to say the least.

Merced can have a ton of outstanding accesses at a time, but that's a different architecture.

<I think that K7 uses the same motherboard as Alpha, but my information is strictly hearsay.>

I wouldn't be surprised if the first K7 systems are built around "borrowed" Alpha motherboards, but they'll have to slow the processor bus down to 200 MHz from the current 333 MHz speed.

Tenchusatsu
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