Starc consortium proposes 0.10-micron process standards
By Paul Kallender
EE Times
(08/24/01 11:24 a.m. EST)
TOKYO — Japan's semiconductor research consortium released its recommended design rules for 0.10-micron technology on Thursday (Aug. 23), and outlined a road map toward a common intellectual-property (IP) library to help Japan's struggling semiconductor industry build common platforms on which to produce system-on-chip devices faster and more cheaply. The consortium's goal is to have all chip makers in Japan and around the world embrace its process standards.
The Semiconductor Technology Academic Research Center (Starc), an industrial consortium responsible for promoting standardized process technologies, has set voltage, physical gate length, poly and metal pitch standards for high performance and "middle" performance, running down to 1 volt with physical gate lengths at 0.065 micron.
The voltages set for standard operation of transistors is 1, 2.5 and 3.3 V. Poly pitch sizes were set at 0.24 micron and first-layer metal pitches are at 0.28 micron.
"We believe this will not only help standardization in Japan but throughout the world. We are very happy about this," Toyoki Takemoto, Starc's chief operating officer and executive vice president, told EE Times.
Japan needs to address the huge and widening gap that has emerged since the mid-1990s between chip transistor density and integration levels, said Tadahiko Nakamura, senior manager of Starc's IP-reuse group. Following one of the implications of Moore's Law, transistor density has been rising an average of 58 percent a year since 1995, he said. Integration simply has not kept pace.
While Intel Corp., for one, is attacking the problem by developing cores that use more software layers, Japan needs to promote a revolution in system-on-chip integration capabilities built on common process technologies and buttressed by IP sharing, said Nakamura.
IP library program
In pursuit of that goal, he said, Starc will make available about 500 libraries of IP this year. Those libraries should triple in size as the consortium introduces a number of innovations, Nakamura said.
By spring of next year, he said, Starc will have finished an e-commerce-type Internet-based IP information-exchange system, somewhat similar to the Virtual Socket Interface Alliance's IP description standard. Starc's templates will enable engineers to talk to each other in HDL. A common quality-guarantee standard will also come next spring, Nakamura said, and by next summer, Starc will finish a common interface standard for rapid checking.
"This equals FPGA technology, where we can standardize for the emulator companies. We think the end users will be very pleased about this," he said.
The consortium posted its 0.13-micron process recommendations last October, well behind many of its members' individual platforms. Starc's members consist of Japan's big-five integrated device manufacturers — Toshiba, NEC, Mitsubishi, Hitachi and Fujitsu — plus virtually every other electronics powerhouse here, including Matsushita, Sony, Sanyo and Sharp. Rohm, Oki Electric and Seiko Epson are also members.
Getting all these companies to work together to promote a common 0.13-micron standard proved a useful trial run, Starc's Takemoto said.
Two of the big five chip makers have already announced their own next-generation, proprietary 0.10-micron processes. NEC developed its 100-nanometer UX6 process with Taiwan Semiconductor Manufacturing Co., while Toshiba said this spring it was working with Sony for process technologies down to 70 nm.
"[Standardization] is the first question on people's minds," said Yoshihiro Mabuchi, senior manager of the device-development department at NEC Electron Devices' system LSI design-engineering division. "Our strategy is that we have to promote standardization and our objectives are the same as Starc's. Our UX6 process is almost the same as Starc's and right now we are studying the possibility of creating a common library between the two processes."
Altered specs
Fujitsu, for its part, fully backs the common process led by Starc, said Koichi Fujita, general manager of Fujitsu Ltd.'s advanced CMOS technology semiconductor group. Fujitsu has altered specs on its own 100-nm process to bring them in line with Starc's, and Hitachi is believed to have done the same, he said.
"Our design is very similar to NEC's and Starc's, so we decided to change our rules to be in compliance with Starc's," Fujita said. "The changes were very minor." Fujitsu will reveal details of its process at the end of this year, or the beginning of next year at the latest, he added.
Nakamura said that Toshiba too is backing Starc's standards
At the 0.10-micron level, Starc was on time and had all members in the same boat, pulling together, said Takemoto.
"Several companies have announced their 0.10-micron design rules over the past three months, but the important thing to remember is, this time fully 12 Japanese companies have clearly stated that they will go together to standardize the design rule and IP and IP-reuse issues," Takemoto said.
"We realize that members have to develop very specific technologies for their key customers and they have a right to make them," said Nakamura. "If NEC gets a special customer, they can use their proprietary solution. If Sony asks Toshiba for a special solution, that's fine. The problem is that not many customers will ask for huge quantities. We admire those companies that can pick up business like that, but we are also [in need of] common business models and standardized rules." |
