HOT NEW NEWS on MERCED CHIP (well better than INTC $.88):
HP and Intel Unveil Breakthrough EPIC Technology at Microprocessor Forum;
First Glimpse of Future 64-bit Technologies That Lay the Groundwork for IA-64
BusinessWire, Tuesday, October 14, 1997 at 17:17
SAN JOSE, Calif.--(BUSINESS WIRE)--Oct. 14, 1997--Today
Hewlett-Packard Company and Intel Corporation revealed the first
details of their jointly defined Explicitly Parallel Instruction
Computing (EPIC) technology, the foundation for the new 64-bit
Instruction Set Architecture (ISA).
The 64-bit ISA is the definition of the software instructions
that drive the flow of operations within the microprocessor. EPIC
will deliver a breakthrough in microprocessor technology, enabling
industry-leading performance, compatibility and scalability, thereby
addressing the next-generation 64-bit high-end workstation and server
market requirements.
Today's joint presentation outlined technical concepts of the new
EPIC technology and discussed key features of the 64-bit ISA built on
these concepts. EPIC, incorporating an innovative and unique
combination of speculation, predication and explicit parallelism, is
expected to advance the state of the art in processor technologies,
specifically addressing the performance limitations found in today's
RISC (Reduced Instruction Set Computing) and CISC (Complex
Instruction Set Computing) technologies.
EPIC technology breaks through the sequential nature of today's
conventional processor architectures by allowing the software to
communicate explicitly to the processor when operations can be done
in parallel. Increased performance is realized by reducing the
number of branches and branch mispredicts, and reducing the effects
of memory-to-processor latency. The future 64-bit Intel Architecture
(IA-64) applies EPIC technology to deliver explicit parallelism,
massive resources and inherent scalability not available with
conventional RISC architectures.
"As future 64-bit microprocessors attempt to deliver more
parallelism, performance limiters such as branches, memory latency
and today's sequential programming model will become even more
significant issues," said John Crawford, Intel fellow and director,
Microprocessor Architecture, Intel Corporation.
"EPIC technology was developed to address these issues and enable
IA-64, using the jointly developed 64-bit ISA to deliver world class
performance and computing headroom. Intel's IA-64 processors will
provide performance and features required to address the needs of
high-end servers and workstations, along with full compatibility for
IA-32 applications and operating systems."
"The jointly defined 64-bit instruction set architecture will
ultimately enable a new level of system performance," said Jerry
Huck, project manager and lead architect at HP's Systems Architecture
and Design Lab. "This next-generation ISA uses predication,
speculation and explicit parallelism to overcome the performance
constraints of conventional RISC architectures. HP systems based on
the IA-64 will surpass the performance of today's systems while
protecting customers' software investments by remaining
backward-compatible."
HP and Intel announced their joint research-and-development
project in June of 1994. Aimed at providing advanced technologies
for end-of-the-decade workstation, server and enterprise-computing
products, the two companies' efforts include development of the
64-bit ISA and compiler optimization.
The first microprocessor based on IA-64 -- code-named Merced --
is an Intel product being designed, manufactured and marketed by
Intel, and is scheduled for production in 1999.
HP is the official information-technology hardware and
maintenance supplier to the 1998 World Cup soccer tournament and the
1997 Tournament of France. Selected for its technology and skills to
support and manage mission-critical applications, HP will help create
an information-management infrastructure for handling game-scoring;
media centers; personnel accreditation; hotel information; and
various ticketing, stadium, warehouse and back-office operations.
Hewlett-Packard Company is a leading global provider of
computing, Internet and intranet solutions, services, communications
products and measurement solutions, all of which are recognized for
excellence in quality and support. It is the second-largest computer
supplier in the United States, with computer-related revenue in
excess of $31.4 billion in its 1996 fiscal year. HP has 120,500
employees and had revenue of $38.4 billion in its 1996 fiscal year.
Information about HP and its products can be found on the World Wide
Web at www.hp.com .
Intel, the world's largest chip maker, is also a leading
manufacturer of personal computer, networking and communications
products. Additional information is available at
www.intel.com/pressroom .
Note To Editors: Third party marks and brands are property of
their respective holders.
Glossary of Terms
-- branches: The "forks in the road" of a program at which a
decision is made regarding the correct path to take to continue.
-- CISC: complex instruction set computer
-- compiler: A tool that translates a programmer's high-level
instructions into the language of the microprocessor.
-- EPIC (Explicitly Parallel Instruction Computing): The new
"architecture technology" that was jointly defined by Intel and HP
(analogous to RISC and CISC). It will be the foundation for the new
64-bit Instruction Set Architecture.
-- explicit parallelism: The ability of the compiler to directly
inform the processor of the independent nature of operations.
-- IA-32 (Intel 32-bit Architecture): Intel's volume processor
product family, addressing computing requirements for desktop,
mobile, servers and workstations.
-- IA-64 (Intel 64-bit Architecture): The Intel 64-bit
Architecture implements EPIC concepts using the jointly developed
64-bit Instruction Set Architecture in addition to full IA-32
compatibility.
-- implicit parallelism: Found in conventional microprocessor
architectures, this requires the compiler to create sequential
machine code that can interact with the processor.
-- ISA (Instruction Set Architecture): The operating instructions
that tell a chip how to perform software functions and direct
operations within the microprocessor. HP and Intel jointly developed
a new 64-bit ISA. This ISA integrates technical concepts from the
EPIC technology.
-- memory latency: The time it takes for the data to arrive from
memory to the processor after the processor has requested it.
-- Merced(TM) processor: The first processor from Intel in the IA-64
family.
-- mispredicts: A wrong decision regarding which path to take.
-- parallelism: The ability to execute multiple instructions at the
same time (vs. sequentially, which is one after the other).
-- predication: A technical concept that contributes to increasing
overall performance by the removal of branches and associated
mispredicts.
-- RISC: reduced instruction set computer
-- speculation: A method to initiate a request for information,
even before it is definitely known that the information will be
needed.
CONTACT: Intel Corporation
Marion Koehler, 408/765-3547
marion_koehler@ccm.sc.intel.com
or
Copithorne & Bellows (for Hewlett-Packard)
Darleen Anderson, 415/975-2239
darleen.anderson@cbpr.com
KEYWORD: CALIFORNIA
INDUSTRY KEYWORD: COMPUTERS/ELECTRONICS COMED TELECOMMUNICATIONS
INTERACTIVE/MULTIMEDIA/INTERNET PRODUCT TRADESHOW
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