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Politics : Formerly About Applied Materials
AMAT 240.80+4.6%Nov 5 3:59 PM EST

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To: James Calladine who wrote (53482)10/1/2001 9:45:10 AM
From: Proud_Infidel   of 70976
 
Chartered pulls up 0.10-micron foundry targets, plans prototyping in late 2002

Singapore foundry company accelerates mixed-signal module to be available in Q1 of 2003
Semiconductor Business News
(10/01/01 08:59 a.m. EST)


SAN JOSE -- Singapore's Chartered Semiconductor Manufacturing Pte. Ltd. this week will unveil its accelerated 0.10-micron technology roadmap during a company forum here, promising to begin silicon-foundry prototyping services for the next-generation digital CMOS copper processes in the second half of 2002.

To strengthen its position in the next technology node, the world's third largest pure-play chip foundry aims to move up availability of 0.10-micron mixed-signal process modules by about three months and begin prototyping services for those ICs in the first quarter of 2003, said Chartered managers prior to Thursday's rollout.

Chartered is also moving up its milestones for "alpha" level pre-silicon qualification of electronic design automation and third-party intellectual property (IP) cores and libraries. The 0.10-micron process specifications and device structures will be available from EDA, IP and design library partners in the first quarter of 2002, said Michael Buehler-Garcia, vice president or marketing and worldwide EDA services at Chartered.

"That's about six months earlier than the prior process generation," said Chartered's EDA vice president, based in Milpitas, Calif. "We providing the EDA and design core partners with pre-silicon proven TCAD [technology computer-aided design modules] to get them started earlier in supporting the 0.10-micron processes."

Chartered's early design partners in 0.10-micron (100-nm) processes are: Artisan Components Inc. and Avanti Corp. for baseline CMOS tools, Cadence Design Systems Inc. for mixed-signal tools, and Virage Logic Corp. for embedded memories. The pre-silicon release of Chartered's 0.10-micron design kits and models are now set for the first quarter of 2002.

To address silicon-on-chip (SoC) designs--especially ICs used in communications applications--Chartered has accelerated its goals for initial prototyping services with mixed-signal modules from an original target of mid-2003 to the first quarter of that year.

"The acceleration of the mixed-signal module is a result of customers asking for SoC products and needing mixed-signal [analog and digital blocks] to talk to the real world in communications applications," Buehler-Garcia said. "Last year, we stood up at this forum [in San Jose] and rolled out the 0.13-micron milestones. This year, we will be presenting data to show we are meeting those milestones, and we'll be doing it again for 0.1-micron," he said, referring to Chartered's technology forum at the Doubletree Hotel in San Jose on Thursday.
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