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Politics : Formerly About Advanced Micro Devices
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To: Process Boy who wrote (62234)6/18/1999 2:00:00 PM
From: Shane Geary   of 1576093
 
PB: Re: " TSMC goes with a relatively larger Leff to minimize gate leakage. Another approach is to (obviously?) optimize the isolation structures"

Are we talking about the same thing here? To me, gate leakage is a leakage current through the gate oxide, rather than sub-threshold current between source and drain.

Anyway, we are is severe danger of going off-topic here (well, too late I suppose) and boring people to death, even if anyone is reading.

Yousef has a lot to answer for, for starting this off.

Regards,

Shane
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