ARM and Cadence Establish New Five-Year Agreement Targeting Design Chain Optimization
Tuesday March 4, 9:04 am ET
SAN JOSE, Calif. & CAMBRIDGE, England--(BUSINESS WIRE)--March 4, 2003--
Collaboration to Accelerate Mutual Customers' Design-To-Volume, Built on Previous Success of More Than 30 ARM Core-based SoCs
Cadence Design Systems, Inc. (NYSE:CDN - News), and ARM(LSE:ARM - News; Nasdaq:ARMHY - News), the industry's leading provider of 16/32-bit embedded RISC processor solutions, today announced at D.A.T.E., in Munich, a new five-year agreement targeting design chain optimization for their mutual customers. With this agreement, ARM is providing direct access to ARM intellectual property (IP) to facilitate optimization of design and verification solutions from Cadence on ARM® core-based SoCs.
The cooperation between ARM and Cadence will enable customers to incorporate different ARM cores into the newly announced Cadence® Incisive(TM) verification platform for high-speed verification. As a result, customers will be able to build systems with verified, reusable hardware and software IP blocks faster and with greater confidence that the systems will be manufacturable the first time.
"In today's SoC design environment, reusable IP and design tools need to work 'hand-in-glove' to create design consistency and repeatability in as short a time as possible. It is no longer possible to get premium performance from the latest IP without working with the EDA vendors simultaneously," said Mike Inglis, executive vice president of marketing at ARM. "This new agreement will enable Cadence to leverage access to our IP for the benefit of our mutual customers, enabling a better SoC design experience."
This agreement builds on the companies' existing cooperation on verification, verification acceleration/emulation, signal integrity and design services. Cadence was the first member of ATAP(TM), the ARM technology access program, and has delivered more than 30 successful tape-outs of ARM Powered® designs through its Design Foundry services business. The two companies are currently working on improving design chain interoperability via standardized models and validation suites for ARM's AMBA bus using the SystemC modeling language.
"STEPMIND designs and delivers some of the most innovative systems on the market today for GSM/GPRS/EDGE, like the GSM/GPRS/EDGE baseband processor and four-band GSM RF transceiver. Our design-to-volume will benefit immensely from this alliance," said Alain Jolivet, chairman of STEPMIND. "The combination of pre-verified ARM IP and Cadence software will reduce the risks and turnaround time for our customers, and provide us with the comprehensive, best-in-class SoC design and verification solutions we need."
Planned deliverables of this collaboration include Cadence Incisive verification tools combined with the ARM Integrator(TM) Logic Tile products for acceleration/emulation, and Cadence signal integrity solutions combined with ARM signal integrity libraries for specific foundries. The results will benefit systems designers such as architects, hardware verification engineers and software developers, fabless designers and integrated device manufacturers (IDMs).
"ARM is one of the pre-eminent suppliers of IP cores for a significant proportion of Atmel's system-on-chip products," said Michel Guellec, IP integration manager at Atmel. "The agreement between ARM and Cadence gives us confidence in continuing to be able to supply right-first-time silicon as we move into nanoscale technology."
"We are enthusiastic about the growing collaboration between ARM and Cadence. We are committed to optimizing the industry design chain to accelerate our customers' design-to-volume," said Penny Herscher, executive vice president and chief marketing officer at Cadence. "This agreement will enable our customers to take full advantage of our advanced technology when designing with ARM IP." |
